mirror of
https://github.com/mpv-player/mpv
synced 2025-03-09 23:58:06 +00:00
upgraded to newest vidix interface
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4328 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
alex
parent
c5c4f37195
commit
cf9d77fba1
@ -11,13 +11,34 @@
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#include "../../libdha/pci_ids.h"
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#include "../../libdha/pci_names.h"
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//#include "nvidia.h"
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#include "nvidia.h"
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static void *mmio_base = 0;
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static void *mem_base = 0;
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static void *ctrl_base = 0;
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static void *fb_base = 0;
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static int32_t overlay_offset = 0;
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static uint32_t ram_size = 0;
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static unsigned int *PFB;
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static unsigned int *PCIO;
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static unsigned int *PGRAPH;
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static unsigned int *PRAMIN;
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static unsigned int *FIFO;
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static unsigned int *PMC;
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typedef unsigned char U008;
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#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
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unsigned int nv_fifo_space = 0;
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void CRTCout(unsigned char index, unsigned char val)
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{
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NV_WR08(PCIO, 0x3d4, index);
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NV_WR08(PCIO, 0x3d5, val);
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}
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volatile RivaScaledImage *ScaledImage;
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#define CARD_FLAGS_NONE 0x00
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#define CARD_FLAGS_NOTSUPPORTED 0x01
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@ -29,6 +50,8 @@ struct nv_card_id_s
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const int flags;
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};
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static const struct nv_card_id_s nv_card_id;
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static const struct nv_card_id_s nv_card_ids[]=
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{
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{ DEVICE_NVIDIA_RIVA_TNT2_NV5, "nVidia TNT2 (NV5) ", 5, CARD_FLAGS_NOTSUPPORTED},
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@ -54,10 +77,11 @@ static int probed = 0;
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static vidix_capability_t nvidia_cap =
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{
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"NVIDIA driver for VIDIX",
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"alex",
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TYPE_OUTPUT,
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{ 0, 0, 0, 0 },
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1024,
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768,
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2046,
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2047,
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4,
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4,
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-1,
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@ -108,6 +132,8 @@ int vixProbe(int verbose,int force)
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else
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printf("Found chip: %s\n", nv_card_ids[idx].name);
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memcpy(&nv_card_id, &nv_card_ids[idx], sizeof(struct nv_card_id_s));
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nvidia_cap.device_id = nv_card_ids[idx].id;
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err = 0;
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memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
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@ -132,20 +158,99 @@ int vixProbe(int verbose,int force)
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int vixInit(void)
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{
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int card_option;
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printf("[nvidia] init\n");
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pci_config_read(pci_info.bus, pci_info.card, pci_info.func, 0x40,
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4, &card_option);
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printf("card_option: %x\n", card_option);
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if (!probed)
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{
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printf("Driver was not probed but is being initialized\n");
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return(EINTR);
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}
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mmio_base = map_phys_mem(pci_info.base0, 0xFFFF);
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if (mmio_base == (void *)-1)
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ctrl_base = map_phys_mem(pci_info.base0, 0x00800000);
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if (ctrl_base == (void *)-1)
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return(ENOMEM);
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fb_base = map_phys_mem(pci_info.base1, 0x01000000);
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if (fb_base == (void *)-1)
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return(ENOMEM);
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printf("mmio_base: %p\n", mmio_base);
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return ENXIO;
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printf("ctrl_base: %p, fb_base: %p\n", ctrl_base, fb_base);
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PFB = ctrl_base+0x00100000;
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PGRAPH = ctrl_base+0x00400000;
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PRAMIN = ctrl_base+0x00710000;
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FIFO = ctrl_base+0x00800000;
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PCIO = ctrl_base+0x00601000;
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PMC = ctrl_base+0x00000000;
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printf("pfb: %p, pgraph: %p, pramin: %p, fifo: %p, pcio: %p\n",
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PFB, PGRAPH, PRAMIN, FIFO, PCIO);
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ScaledImage = FIFO+0x8000/4;
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printf("ScaledImage: %p\n", ScaledImage);
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/* unlock */
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CRTCout(0x11, 0xff);
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printf("fifo_free: %d\n", ScaledImage->fifo_free);
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RIVA_FIFO_FREE(ScaledImage, 10);
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dump_scaledimage(ScaledImage);
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/* create scaled image object */
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*(PRAMIN+0x518) = 0x0100A037;
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*(PRAMIN+0x519) = 0x00000C02;
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/* put scaled image object into subchannel */
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*(FIFO+0x2000) = 0x80000011;
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/* ram size detection */
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switch(nv_card_id.core)
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{
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case 5:
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{
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if (*(PFB+0x0) & 0x00000100)
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{
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printf("first ver\n");
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ram_size = ((*(PFB+0x0) >> 12) & 0x0f) * 1024 * 2 + 1024 * 2;
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}
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else
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{
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printf("second ver (code: %d)\n",
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*(PFB+0x0) & 0x00000003);
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switch(*(PFB+0x0) & 0x00000003)
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{
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case 0:
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ram_size = 1024*32;
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break;
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case 1:
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ram_size = 1024*4;
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break;
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case 2:
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ram_size = 1024*8;
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break;
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case 3:
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ram_size = 1024*16;
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break;
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default:
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printf("Unknown ram size code: %d\n",
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*(PFB+0x0) & 0x00000003);
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break;
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}
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}
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break;
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}
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default:
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printf("Unknown core: %d\n", nv_card_id.core);
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}
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printf("ram_size: %d\n", ram_size);
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return 0;
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}
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void vixDestroy(void)
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@ -162,16 +267,49 @@ int vixGetCapability(vidix_capability_t *to)
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int vixQueryFourcc(vidix_fourcc_t *to)
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{
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printf("[nvidia] query fourcc (%x)\n", to->fourcc);
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to->flags = 0;
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to->depth = VID_DEPTH_32BPP;
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return 0;
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}
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int vixConfigPlayback(vidix_playback_t *info)
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{
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int fb_pixel_size = 32/8;
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int fb_line_len = 1280*4;
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char buffer = 0;
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int offset = 0;
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int x,y,h,w;
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int bpp = 32 >> 3;
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int size;
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printf("[nvidia] config playback\n");
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info->num_frames = 2;
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x = info->src.x;
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y = info->src.y;
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h = info->src.h;
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w = info->src.w;
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w = (w + 1) & ~1;
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size = h * (((w << 1) + 63) & ~63) / bpp;
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PMC[(0x8900/4)+buffer] = offset;
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PMC[(0x8928/4)+buffer] = (h << 16) | w;
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PMC[(0x8930/4)+buffer] = ((y << 4) & 0xffff0000) | (x >> 12);
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PMC[(0x8938/4)+buffer] = (w << 20) / info->dest.w;
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PMC[(0x8938/4)+buffer] = (h << 20) / info->dest.h;
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info->dga_addr = fb_base + (info->dest.w - info->src.w) * fb_pixel_size /
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2 + (info->dest.h - info->src.h) * fb_line_len / 2;
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info->num_frames = 1;
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info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2;
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info->dga_addr = malloc(info->num_frames*info->frame_size);
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info->offsets[0] = 0;
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info->offset.y = 0;
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info->offset.v = ((info->src.w + 31) & ~31) * info->src.h;
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info->offset.u = info->offset.v+((info->src.w + 31) & ~31) * info->src.h / 4;
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// info->dga_addr = malloc(info->num_frames*info->frame_size);
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return 0;
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}
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@ -609,6 +609,7 @@ vidix_capability_t def_cap =
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#else
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"BES driver for radeon cards",
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#endif
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"Nick Kurshev",
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TYPE_OUTPUT | TYPE_FX,
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{ 0, 0, 0, 0 },
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2048,
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