From ce74aa0e963cd0451efbc97d02dd423f9a1dbd45 Mon Sep 17 00:00:00 2001
From: reimar <reimar@b3059339-0415-0410-9bf9-f77b7e298cf2>
Date: Sun, 28 Nov 2010 07:47:37 +0000
Subject: [PATCH] vidix: radeon and big-endian fixes

Add R_OVL_SHIFT to all R280 devices. Only actually confirmed for two.
Fixes bug #1826.

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@32663 b3059339-0415-0410-9bf9-f77b7e298cf2

Restore big-endian support removed in thoughtless upstream merge
at r23062.

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@32664 b3059339-0415-0410-9bf9-f77b7e298cf2

100l, fix vidix compilation on big-endian

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@32665 b3059339-0415-0410-9bf9-f77b7e298cf2

Add horrible hack to make xvidix work on big-endian.

git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@32666 b3059339-0415-0410-9bf9-f77b7e298cf2
---
 vidix/radeon.h     |  2 ++
 vidix/radeon_vid.c | 58 +++++++++++++++++++++++++++++++++++++++-------
 2 files changed, 51 insertions(+), 9 deletions(-)

diff --git a/vidix/radeon.h b/vidix/radeon.h
index f7b07914d8..733c028a39 100644
--- a/vidix/radeon.h
+++ b/vidix/radeon.h
@@ -77,6 +77,8 @@
 #define	I2C_DATA				0x0098
 #define	CONFIG_CNTL				0x00E0
 /* CONFIG_CNTL bit constants */
+#       define APER_0_BIG_ENDIAN_16BPP_SWAP     0x00000001
+#       define APER_0_BIG_ENDIAN_32BPP_SWAP     0x00000002
 #	define CFG_VGA_RAM_EN			0x00000100
 #ifdef RAGE128
 #define GEN_RESET_CNTL				0x00f0
diff --git a/vidix/radeon_vid.c b/vidix/radeon_vid.c
index ee8aa23109..ee68653c2c 100644
--- a/vidix/radeon_vid.c
+++ b/vidix/radeon_vid.c
@@ -394,15 +394,16 @@ static const ati_card_ids_t ati_card_ids[] =
  { DEVICE_ATI_RADEON_R250_LG,		R_250|R_OVL_SHIFT },
  { DEVICE_ATI_RV250_RADEON_9000,	R_250|R_OVL_SHIFT },
  { DEVICE_ATI_RADEON_RV250_RADEON2,	R_250|R_OVL_SHIFT },
- { DEVICE_ATI_RV280_RADEON_9200,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92002,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92003,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92004,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92005,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92006,	R_280 },
- { DEVICE_ATI_RV280_RADEON_92007,	R_280 },
- { DEVICE_ATI_M9_5C61_RADEON,		R_280 },
- { DEVICE_ATI_M9_5C63_RADEON,		R_280 },
+ // Only 92006 and 92007 tested to actually require this
+ { DEVICE_ATI_RV280_RADEON_9200,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92002,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92003,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92004,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92005,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92006,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_RV280_RADEON_92007,	R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_M9_5C61_RADEON,		R_280|R_OVL_SHIFT },
+ { DEVICE_ATI_M9_5C63_RADEON,		R_280|R_OVL_SHIFT },
 /* Radeon3 (indeed: Rage 1024 Pro ;) */
  { DEVICE_ATI_R300_AG_FIREGL,		R_300 },
  { DEVICE_ATI_RADEON_R300_ND,		R_300 },
@@ -1267,6 +1268,7 @@ typedef struct saved_regs_s
     uint32_t ov0_graphics_key_msk;
     uint32_t ov0_key_cntl;
     uint32_t disp_merge_cntl;
+    uint32_t config_cntl;
 }saved_regs_t;
 static saved_regs_t savreg;
 
@@ -1279,6 +1281,13 @@ static void save_regs( void )
     savreg.ov0_graphics_key_msk = INREG(OV0_GRAPHICS_KEY_MSK);
     savreg.ov0_key_cntl		= INREG(OV0_KEY_CNTL);
     savreg.disp_merge_cntl	= INREG(DISP_MERGE_CNTL);
+#if HAVE_BIGENDIAN
+#ifdef RAGE128
+    savreg.config_cntl          = INREG(CONFIG_CNTL);
+#else
+    savreg.config_cntl          = INREG(SURFACE_CNTL);
+#endif
+#endif
 }
 
 static void restore_regs( void )
@@ -1290,6 +1299,31 @@ static void restore_regs( void )
     OUTREG(OV0_GRAPHICS_KEY_MSK,savreg.ov0_graphics_key_msk);
     OUTREG(OV0_KEY_CNTL,savreg.ov0_key_cntl);
     OUTREG(DISP_MERGE_CNTL,savreg.disp_merge_cntl);
+#if HAVE_BIGENDIAN
+#ifdef RAGE128
+    OUTREG(CONFIG_CNTL, savreg.config_cntl);
+#else
+    OUTREG(SURFACE_CNTL, savreg.config_cntl);
+#endif
+#endif
+}
+
+/**
+ * Clear swap bits of surface data control regs for bigendian
+ */
+static void clear_swap(void)
+{
+#if HAVE_BIGENDIAN
+#ifdef RAGE128
+   OUTREG(CONFIG_CNTL,
+          savreg.config_cntl &
+          ~(APER_0_BIG_ENDIAN_16BPP_SWAP | APER_0_BIG_ENDIAN_32BPP_SWAP));
+#else
+   OUTREG(SURFACE_CNTL,
+          savreg.config_cntl &
+          ~(NONSURF_AP0_SWP_32BPP | NONSURF_AP0_SWP_16BPP));
+#endif
+#endif
 }
 
 static int radeon_init(void)
@@ -1351,6 +1385,7 @@ static int radeon_init(void)
   }
 #endif
   save_regs();
+  clear_swap();
   return 0;
 }
 
@@ -3150,6 +3185,11 @@ static int radeon_frame_select(unsigned frame)
 {
     uint32_t off[6];
     int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs;
+    // This really only needs to be set during data writes,
+    // however we don't have a hook there.
+    // The setup at startup is not enough since X11 regularly
+    // resets this to values to the wrong values for us.
+    clear_swap();
     /*
     buf3-5 always should point onto second buffer for better
     deinterlacing and TV-in