mirror of
https://github.com/mpv-player/mpv
synced 2025-01-31 04:02:06 +00:00
updated the ati vidix driver with the one from upstream vidix, it now supports much more GPUs (including all Radeon > 9600 and X series)
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@23062 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
ben
parent
c7a0712f30
commit
be94988aa9
@ -148,13 +148,23 @@
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#define AIC_TLB_DATA 0x01E8
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#define DAC_CNTL 0x0058
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/* DAC_CNTL bit constants */
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# define DAC_RANGE_CNTL_MSK 0x00000003
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# define DAC_RANGE_PAL 0x00000000
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# define DAC_RANGE_NTSC 0x00000001
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# define DAC_RANGE_PS2 0x00000002
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# define DAC_BLANKING 0x00000004
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# define DAC_CMP_EN 0x00000008
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# define DAC_CMP_OUTPUT 0x00000080
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# define DAC_8BIT_EN 0x00000100
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# define DAC_4BPP_PIX_ORDER 0x00000200
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# define DAC_TVO_EN 0x00000400
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# define DAC_TVO_OVR_EXCL 0x00000800
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# define DAC_TVO_16BPP_DITH_EN 0x00001000
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# define DAC_VGA_ADR_EN (1 << 13)
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# define DAC_PWDN (1 << 15)
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# define DAC_CRC_EN 0x00080000
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# define DAC_MASK_ALL (0xff << 24)
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# define DAC_VGA_ADR_EN (1 << 13)
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# define DAC_RANGE_CNTL (3 << 0)
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# define DAC_BLANKING (1 << 2)
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#define DAC_CNTL2 0x007c
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/* DAC_CNTL2 bit constants */
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# define DAC2_DAC_CLK_SEL (1 << 0)
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@ -191,6 +201,7 @@
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# define CRTC2_DISP_DIS (1 << 23)
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# define CRTC2_EN (1 << 25)
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# define CRTC2_DISP_REQ_EN_B (1 << 26)
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# define CRTC2_CSYNC_EN (1 << 27)
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# define CRTC2_HSYNC_DIS (1 << 28)
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# define CRTC2_VSYNC_DIS (1 << 29)
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#define MEM_CNTL 0x0140
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@ -284,6 +295,19 @@
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# define CRTC_DISPLAY_DIS_BYTE (1 << 2)
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#define RB3D_CNTL 0x1C3C
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#define WAIT_UNTIL 0x1720
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# define EVENT_CRTC_OFFSET 0x00000001
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# define EVENT_RE_CRTC_VLINE 0x00000002
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# define EVENT_FE_CRTC_VLINE 0x00000004
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# define EVENT_CRTC_VLINE 0x00000008
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# define EVENT_BM_VIP0_IDLE 0x00000010
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# define EVENT_BM_VIP1_IDLE 0x00000020
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# define EVENT_BM_VIP2_IDLE 0x00000040
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# define EVENT_BM_VIP3_IDLE 0x00000080
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# define EVENT_BM_VIDCAP_IDLE 0x00000100
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# define EVENT_BM_GUI_IDLE 0x00000200
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# define EVENT_CMDFIFO 0x00000400
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# define EVENT_OV0_FLIP 0x00000800
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# define EVENT_CMDFIFO_ENTRIES 0x07F00000
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#define ISYNC_CNTL 0x1724
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#define RBBM_GUICNTL 0x172C
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#define RBBM_STATUS 0x0E40
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@ -563,7 +587,7 @@
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# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */
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# define SCALER_ADAPTIVE_DEINT 0x00001000L
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# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
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# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */
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# define SCALER_USE_OV1 0x00004000L /* Use/force Ov1 instead of Ov0 */
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# define SCALER_SMART_SWITCH 0x00008000L
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#ifdef RAGE128
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# define SCALER_BURST_PER_PLANE 0x00ff0000L
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@ -574,9 +598,7 @@
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# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */
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# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */
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# define SCALER_DIS_LIMIT 0x08000000L
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#ifdef RAGE128
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# define SCALER_PRG_LOAD_START 0x10000000L
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#endif
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# define SCALER_INT_EMU 0x20000000L
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# define SCALER_ENABLE 0x40000000L
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# define SCALER_SOFT_RESET 0x80000000L
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@ -599,32 +621,32 @@
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#define OV0_VID_BUF0_BASE_ADRS 0x0440
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# define VIF_BUF0_PITCH_SEL 0x00000001L
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# define VIF_BUF0_TILE_ADRS 0x00000002L
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# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF0_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF1_BASE_ADRS 0x0444
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# define VIF_BUF1_PITCH_SEL 0x00000001L
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# define VIF_BUF1_TILE_ADRS 0x00000002L
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# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF1_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF2_BASE_ADRS 0x0448
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# define VIF_BUF2_PITCH_SEL 0x00000001L
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# define VIF_BUF2_TILE_ADRS 0x00000002L
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# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF2_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF3_BASE_ADRS 0x044C
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# define VIF_BUF3_PITCH_SEL 0x00000001L
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# define VIF_BUF3_TILE_ADRS 0x00000002L
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# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF3_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF4_BASE_ADRS 0x0450
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# define VIF_BUF4_PITCH_SEL 0x00000001L
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# define VIF_BUF4_TILE_ADRS 0x00000002L
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# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF4_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF5_BASE_ADRS 0x0454
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# define VIF_BUF5_PITCH_SEL 0x00000001L
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# define VIF_BUF5_TILE_ADRS 0x00000002L
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# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L
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# define VIF_BUF5_BASE_ADRS_MASK 0x0ffffff0L
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# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L
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#define OV0_VID_BUF_PITCH0_VALUE 0x0460
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#define OV0_VID_BUF_PITCH1_VALUE 0x0464
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@ -735,6 +757,18 @@
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# define CMP_MIX_OR 0x00000000L
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# define CMP_MIX_AND 0x00000100L
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#define OV0_TEST 0x04F8
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# define OV0_SCALER_Y2R_DISABLE 0x00000001L
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# define OV0_SUBPIC_ONLY 0x00000008L
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# define OV0_EXTENSE 0x00000010L
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# define OV0_SWAP_UV 0x00000020L
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#define OV0_COL_CONV 0x04FC
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# define OV0_CB_TO_B 0x0000007FL
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# define OV0_CB_TO_G 0x0000FF00L
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# define OV0_CR_TO_G 0x00FF0000L
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# define OV0_CR_TO_R 0x7F000000L
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# define OV0_NEW_COL_CONV 0x80000000L
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#define OV1_Y_X_START 0x0600
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#define OV1_Y_X_END 0x0604
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#define OV0_LIN_TRANS_A 0x0D20
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#define OV0_LIN_TRANS_B 0x0D24
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#define OV0_LIN_TRANS_C 0x0D28
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@ -774,9 +808,25 @@
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#define IDCT_CONTROL 0x1FBC
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#define SE_MC_SRC2_CNTL 0x19D4
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# define SECONDARY_SCALE_HACC 0x00001FFFL
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# define SECONDARY_SCALE_VACC 0x0FFF0000L
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# define SECONDARY_SCALE_PICTH_ADJ 0xC0000000L
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#define SE_MC_SRC1_CNTL 0x19D8
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# define SCALE_HACC 0x00001FFFL
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# define SCALE_VACC 0x0FFF0000L
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# define IDCT_EN 0x10000000L
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# define SECONDARY_TEX_EN 0x20000000L
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# define SCALE_PICTH_ADJ 0xC0000000L
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#define SE_MC_DST_CNTL 0x19DC
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# define DST_Y 0x00003FFFL
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# define DST_X 0x3FFF0000L
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# define DST_PITCH_ADJ 0xC0000000L
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#define SE_MC_CNTL_START 0x19E0
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# define SCALE_OFFSET_PTR 0x0000000FL
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# define DST_OFFSET 0x00FFFFF0L
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# define ALPHA_EN 0x01000000L
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# define SECONDARY_OFFSET_PTR 0x1E000000L
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# define MC_DST_HEIGHT_WIDTH 0xE0000000L
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#ifndef RAGE128
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#define SE_MC_BUF_BASE 0x19E4
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#define PP_MC_CONTEXT 0x19E8
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@ -817,6 +867,7 @@
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#define CP_CSQ_CNTL 0x0740
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#define SCRATCH_UMSK 0x0770
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#define SCRATCH_ADDR 0x0774
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#ifndef RAGE128
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#define DMA_GUI_TABLE_ADDR 0x0780
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# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff
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# define DMA_GUI_COMMAND__INTDIS 0x40000000
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@ -832,6 +883,7 @@
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#define DMA_VID_COMMAND 0x07AC
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#define DMA_VID_STATUS 0x07B0
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#define DMA_VID_ACT_DSCRPTR 0x07B4
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#endif
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#define CP_ME_CNTL 0x07D0
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#define CP_ME_RAM_ADDR 0x07D4
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#define CP_ME_RAM_RADDR 0x07D8
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@ -1031,6 +1083,20 @@
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#ifdef RAGE128
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#define GUI_STAT 0x1740
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# define GUI_FIFOCNT_MASK 0x0fff
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# define PM4_BUSY (1 << 16)
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# define MICRO_BUSY (1 << 17)
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# define FPU_BUSY (1 << 18)
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# define VC_BUSY (1 << 19)
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# define IDCT_BUSY (1 << 20)
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# define ENG_EV_BUSY (1 << 21)
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# define SETUP_BUSY (1 << 22)
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# define EDGE_WALK_BUSY (1 << 23)
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# define ADDRESSING_BUSY (1 << 24)
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# define ENG_3D_BUSY (1 << 25)
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# define ENG_2D_SM_BUSY (1 << 26)
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# define ENG_2D_BUSY (1 << 27)
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# define GUI_WB_BUSY (1 << 28)
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# define CACHE_BUSY (1 << 29)
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# define GUI_ACTIVE (1 << 31)
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#endif
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#define SRC_CLUT_ADDRESS 0x1780
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@ -1211,7 +1277,7 @@
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#define RB2D_DSTCACHE_CTLSTAT 0x342C
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#define RB2D_DSTCACHE_MODE 0x3428
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#define BASE_CODE 0x0f0b
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#define BASE_CODE 0x0f0b/*0x0f08*/
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#define RADEON_BIOS_0_SCRATCH 0x0010
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#define RADEON_BIOS_1_SCRATCH 0x0014
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#define RADEON_BIOS_2_SCRATCH 0x0018
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@ -1303,6 +1369,7 @@
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#define PPLL_POST3_DIV_MASK 0x00070000
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/* BUS MASTERING */
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#ifdef RAGE128
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#define BM_FRAME_BUF_OFFSET 0xA00
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#define BM_SYSTEM_MEM_ADDR 0xA04
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#define BM_COMMAND 0xA08
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@ -1338,7 +1405,8 @@
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#define BM_VIDCAP_BUF2 0xA68
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#define BM_VIDCAP_ACTIVE 0xA6c
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#define BM_GUI 0xA80
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#define BM_ABORT 0xA88
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#endif
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/* RAGE THEATER REGISTERS */
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#define DMA_VIPH0_COMMAND 0x0A00
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2569
vidix/radeon_vid.c
2569
vidix/radeon_vid.c
File diff suppressed because it is too large
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