mirror of
https://github.com/mpv-player/mpv
synced 2025-03-25 04:38:01 +00:00
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
sync with mplayerxp git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@6255 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
arpi
parent
b52babace4
commit
ad3d23fcf9
@ -17,6 +17,12 @@ RAGE128_OBJS=rage128_vid.o
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RAGE128_LIBS=-L../../libdha -ldha
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RAGE128_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DRAGE128
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PM3_VID=pm3_vid.so
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PM3_SRCS=pm3_vid.c
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PM3_OBJS=pm3_vid.o
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PM3_LIBS=-L../../libdha -ldha
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PM3_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W
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MACH64_VID=mach64_vid.so
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MACH64_SRCS=mach64_vid.c
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MACH64_OBJS=mach64_vid.o
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@ -47,13 +53,19 @@ MGA_CRTC2_OBJS=mga_crtc2_vid.o
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MGA_CRTC2_LIBS=-L../../libdha -ldha -lm
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MGA_CRTC2_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DCRTC2
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all: $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID)
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all: $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID) $(PM3_VID)
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.SUFFIXES: .c .o
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# .PHONY: all clean
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$(PM3_OBJS): $(PM3_SRCS)
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$(CC) -c $(PM3_CFLAGS) -o $@ $<
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$(PM3_VID): $(PM3_OBJS)
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$(LD) $(PM3_LIBS) -shared -soname $(PM3_VID) -o $(PM3_VID) $(PM3_OBJS)
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$(RADEON_OBJS): $(RADEON_SRCS)
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$(CC) -c $(RADEON_CFLAGS) -o $@ $<
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@ -105,11 +117,15 @@ distclean:
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dep: depend
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depend:
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echo "depend not supported"
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# do nothing here
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install:
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mkdir -p $(BINDIR)
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install -m 755 -s -p *.so $(BINDIR)
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uninstall:
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rm -f $(BINDIR)/*.so
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rmdir -p --ignore-fail-on-non-empty $(BINDIR)
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#
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# include dependency files if they exist
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#
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@ -845,18 +845,19 @@ This means that this sources don't support ISA and VLB cards */
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/* ? 0x80000000ul */
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#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */
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#define BUS_CNTL IOPortTag(0x13u, 0x28u)
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#define BUS_WS 0x0000000ful
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#define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */
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#define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */
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#define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */
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#define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */
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#define BUS_ROM_WS 0x000000f0ul
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#define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */
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#define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */
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#define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */
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#define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */
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#define BUS_ROM_PAGE 0x00000f00ul
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#define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */
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# define BUS_WS 0x0000000ful
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# define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */
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# define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */
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# define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */
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# define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */
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# define BUS_ROM_WS 0x000000f0ul
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# define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */
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# define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */
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# define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */
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# define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */
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# define BUS_ROM_PAGE 0x00000f00ul
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# define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */
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# define BUS_EXT_REG_EN 0x08000000ul
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/* First silicom - Prototype (A11) 0x00000000ul */
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/* Metal mask spin (A12 & A13) 0x00000100ul */
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/* All layer spin (A21) 0x00000200ul */
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@ -1283,20 +1284,24 @@ This means that this sources don't support ISA and VLB cards */
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#define SRC_HEIGHT2 BlockIOTag(0x6bu)
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#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu)
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#define SRC_CNTL BlockIOTag(0x6du)
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#define SRC_PATT_EN 0x00000001ul
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#define SRC_PATT_ROT_EN 0x00000002ul
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#define SRC_LINEAR_EN 0x00000004ul
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#define SRC_BYTE_ALIGN 0x00000008ul
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#define SRC_LINE_X_DIR 0x00000010ul
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#define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */
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#define FAST_FILL_EN 0x00000040ul /* VTB/GTB */
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#define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */
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#define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */
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#define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */
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#define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */
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#define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */
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#define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */
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#define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */
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# define SRC_PATT_EN 0x00000001ul
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# define SRC_PATT_ROT_EN 0x00000002ul
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# define SRC_LINEAR_EN 0x00000004ul
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# define SRC_BYTE_ALIGN 0x00000008ul
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# define SRC_LINE_X_DIR 0x00000010ul
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# define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */
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# define FAST_FILL_EN 0x00000040ul /* VTB/GTB */
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# define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */
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# define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */
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# define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */
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# define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */
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# define BM_OP_FRAME_TO_SYSTEM (0 << 10)
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# define BM_OP_SYSTEM_TO_FRAME (1 << 10)
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# define BM_OP_REG_TO_SYSTEM (2 << 10)
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# define BM_OP_SYSTEM_TO_REG (3 << 10)
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# define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */
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# define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */
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# define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */
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/* ? 0xffff8000ul */
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/* ? BlockIOTag(0x6eu) */
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/* ? BlockIOTag(0x6fu) */
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@ -1348,6 +1353,11 @@ This means that this sources don't support ISA and VLB cards */
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#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */
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#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */
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#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */
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# define CIRCULAR_BUF_SIZE_16KB (0 << 0)
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# define CIRCULAR_BUF_SIZE_32KB (1 << 0)
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# define CIRCULAR_BUF_SIZE_64KB (2 << 0)
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# define CIRCULAR_BUF_SIZE_128KB (3 << 0)
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# define LAST_DESCRIPTOR (1 << 31)
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/* ? BlockIOTag(0x94u) */
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/* ? BlockIOTag(0x95u) */
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/* ? BlockIOTag(0x96u) */
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@ -1409,21 +1419,57 @@ This means that this sources don't support ISA and VLB cards */
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#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */
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#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */
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#define DP_MIX BlockIOTag(0xb5u)
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#define DP_BKGD_MIX 0x0000001ful
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/* ? 0x0000ffe0ul */
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#define DP_FRGD_MIX 0x001f0000ul
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/* ? 0xffe00000ul */
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# define BKGD_MIX_NOT_D (0 << 0)
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# define BKGD_MIX_ZERO (1 << 0)
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# define BKGD_MIX_ONE (2 << 0)
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# define BKGD_MIX_D (3 << 0)
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# define BKGD_MIX_NOT_S (4 << 0)
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# define BKGD_MIX_D_XOR_S (5 << 0)
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# define BKGD_MIX_NOT_D_XOR_S (6 << 0)
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# define BKGD_MIX_S (7 << 0)
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# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0)
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# define BKGD_MIX_D_OR_NOT_S (9 << 0)
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# define BKGD_MIX_NOT_D_OR_S (10 << 0)
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# define BKGD_MIX_D_OR_S (11 << 0)
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# define BKGD_MIX_D_AND_S (12 << 0)
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# define BKGD_MIX_NOT_D_AND_S (13 << 0)
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# define BKGD_MIX_D_AND_NOT_S (14 << 0)
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# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0)
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# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0)
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# define FRGD_MIX_NOT_D (0 << 16)
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# define FRGD_MIX_ZERO (1 << 16)
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# define FRGD_MIX_ONE (2 << 16)
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# define FRGD_MIX_D (3 << 16)
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# define FRGD_MIX_NOT_S (4 << 16)
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# define FRGD_MIX_D_XOR_S (5 << 16)
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# define FRGD_MIX_NOT_D_XOR_S (6 << 16)
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# define FRGD_MIX_S (7 << 16)
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# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16)
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# define FRGD_MIX_D_OR_NOT_S (9 << 16)
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# define FRGD_MIX_NOT_D_OR_S (10 << 16)
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# define FRGD_MIX_D_OR_S (11 << 16)
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# define FRGD_MIX_D_AND_S (12 << 16)
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# define FRGD_MIX_NOT_D_AND_S (13 << 16)
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# define FRGD_MIX_D_AND_NOT_S (14 << 16)
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# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16)
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# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16)
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#define DP_SRC BlockIOTag(0xb6u)
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#define DP_BKGD_SRC 0x00000007ul
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/* ? 0x000000feul */
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#define DP_FRGD_SRC 0x00000700ul
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/* ? 0x0000fe00ul */
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#define DP_MONO_SRC 0x00030000ul
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#define DP_MONO_SRC_ALLONES 0x00000000ul
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#define DP_MONO_SRC_PATTERN 0x00010000ul
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#define DP_MONO_SRC_HOST 0x00020000ul
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#define DP_MONO_SRC_BLIT 0x00030000ul
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/* ? 0xfffc0000ul */
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# define BKGD_SRC_BKGD_CLR (0 << 0)
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# define BKGD_SRC_FRGD_CLR (1 << 0)
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# define BKGD_SRC_HOST (2 << 0)
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# define BKGD_SRC_BLIT (3 << 0)
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# define BKGD_SRC_PATTERN (4 << 0)
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# define BKGD_SRC_3D (5 << 0)
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# define FRGD_SRC_BKGD_CLR (0 << 8)
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# define FRGD_SRC_FRGD_CLR (1 << 8)
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# define FRGD_SRC_HOST (2 << 8)
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# define FRGD_SRC_BLIT (3 << 8)
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# define FRGD_SRC_PATTERN (4 << 8)
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# define FRGD_SRC_3D (5 << 8)
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# define MONO_SRC_ONE (0 << 16)
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# define MONO_SRC_PATTERN (1 << 16)
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# define MONO_SRC_HOST (2 << 16)
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# define MONO_SRC_BLIT (3 << 16)
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#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */
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#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */
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/* ? BlockIOTag(0xb9u) */
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@ -1677,12 +1723,16 @@ This means that this sources don't support ISA and VLB cards */
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#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */
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#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */
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#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */
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#define CMDFIFO_SIZE_MODE 0x00000003ul
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# define CMDFIFO_SIZE_MASK 0x00000003ul
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# define CMDFIFO_SIZE_192 0x00000000ul
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# define CMDFIFO_SIZE_128 0x00000001ul
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# define CMDFIFO_SIZE_64 0x00000002ul
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/* ? 0x0000fffcul */
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#define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */
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#define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */
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# define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */
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# define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */
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/* ? 0xfffc0000ul */
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/* ? BlockIOTag(0x15fu) */
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/* BUS MASTERING */
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#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */
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#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */
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#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */
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@ -1699,6 +1749,14 @@ This means that this sources don't support ISA and VLB cards */
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/* ? BlockIOTag(0x16du) */
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#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */
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#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */
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# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff
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# define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000
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# define DMA_GUI_COMMAND__EOL 0x80000000
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# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0
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# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1
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# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2
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# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3
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# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4
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/* ? BlockIOTag(0x170u) */
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/* ? BlockIOTag(0x171u) */
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/* ? BlockIOTag(0x172u) */
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1113
vidix/drivers/pm3_regs.h
Normal file
1113
vidix/drivers/pm3_regs.h
Normal file
File diff suppressed because it is too large
Load Diff
370
vidix/drivers/pm3_vid.c
Normal file
370
vidix/drivers/pm3_vid.c
Normal file
@ -0,0 +1,370 @@
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/**
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Driver for 3DLabs GLINT R3 and Permedia3 chips.
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Copyright (C) 2002 Måns Rullgård
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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**/
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#include <errno.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include "../vidix.h"
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#include "../fourcc.h"
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#include "../../libdha/libdha.h"
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#include "../../libdha/pci_ids.h"
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#include "../../libdha/pci_names.h"
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#include "../../config.h"
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#include "pm3_regs.h"
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#if 0
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#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__)
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#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__)
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#else
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#define TRACE_ENTER()
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#define TRACE_EXIT()
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#endif
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pciinfo_t pci_info;
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void *pm3_reg_base;
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void *pm3_mem;
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static vidix_capability_t pm3_cap =
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{
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"3DLabs GLINT R3/Permedia3 driver",
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"Måns Rullgård <mru@users.sf.net>",
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TYPE_OUTPUT,
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{ 0, 0, 0, 0 },
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2048,
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2048,
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4,
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4,
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-1,
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FLAG_UPSCALER|FLAG_DOWNSCALER,
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VENDOR_3DLABS,
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-1,
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{ 0, 0, 0, 0 }
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};
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unsigned int vixGetVersion(void)
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{
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return(VIDIX_VERSION);
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}
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static unsigned short pm3_card_ids[] =
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{
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DEVICE_3DLABS_GLINT_R3
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};
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static int find_chip(unsigned chip_id)
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{
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unsigned i;
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for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++)
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{
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if(chip_id == pm3_card_ids[i]) return i;
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}
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return -1;
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}
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int vixProbe(int verbose, int force)
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{
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pciinfo_t lst[MAX_PCI_DEVICES];
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unsigned i,num_pci;
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int err;
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err = pci_scan(lst,&num_pci);
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if(err)
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{
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printf("[pm3] Error occured during pci scan: %s\n",strerror(err));
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return err;
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}
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else
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{
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err = ENXIO;
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for(i=0; i < num_pci; i++)
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{
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if(lst[i].vendor == VENDOR_3DLABS)
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{
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int idx;
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const char *dname;
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idx = find_chip(lst[i].device);
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if(idx == -1)
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continue;
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||||
dname = pci_device_name(VENDOR_3DLABS, lst[i].device);
|
||||
dname = dname ? dname : "Unknown chip";
|
||||
printf("[pm3] Found chip: %s\n", dname);
|
||||
pm3_cap.device_id = lst[i].device;
|
||||
err = 0;
|
||||
memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if(err && verbose) printf("[pm3] Can't find chip\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
#define PRINT_REG(reg) \
|
||||
{ \
|
||||
long _foo = READ_REG(reg); \
|
||||
printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \
|
||||
}
|
||||
|
||||
int vixInit(void)
|
||||
{
|
||||
pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000);
|
||||
pm3_mem = map_phys_mem(pci_info.base2, 0x2000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void vixDestroy(void)
|
||||
{
|
||||
unmap_phys_mem(pm3_reg_base, 0x20000);
|
||||
unmap_phys_mem(pm3_mem, 0x2000000);
|
||||
}
|
||||
|
||||
int vixGetCapability(vidix_capability_t *to)
|
||||
{
|
||||
memcpy(to, &pm3_cap, sizeof(vidix_capability_t));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int is_supported_fourcc(uint32_t fourcc)
|
||||
{
|
||||
switch(fourcc){
|
||||
case IMGFMT_YUY2:
|
||||
case IMGFMT_UYVY:
|
||||
return 1;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int vixQueryFourcc(vidix_fourcc_t *to)
|
||||
{
|
||||
if(is_supported_fourcc(to->fourcc))
|
||||
{
|
||||
to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
|
||||
VID_DEPTH_4BPP | VID_DEPTH_8BPP |
|
||||
VID_DEPTH_12BPP| VID_DEPTH_15BPP|
|
||||
VID_DEPTH_16BPP| VID_DEPTH_24BPP|
|
||||
VID_DEPTH_32BPP;
|
||||
to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
|
||||
return 0;
|
||||
}
|
||||
else to->depth = to->flags = 0;
|
||||
return ENOSYS;
|
||||
}
|
||||
|
||||
#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888
|
||||
#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444
|
||||
#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551
|
||||
#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565
|
||||
#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332
|
||||
#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888
|
||||
#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444
|
||||
#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551
|
||||
#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565
|
||||
#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332
|
||||
#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8
|
||||
#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444
|
||||
#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444
|
||||
#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422
|
||||
#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422
|
||||
|
||||
/* Notice, have to check that we dont overflow the deltas here ... */
|
||||
static void
|
||||
compute_scale_factor(
|
||||
short* src_w, short* dst_w,
|
||||
unsigned int* shrink_delta, unsigned int* zoom_delta)
|
||||
{
|
||||
/* NOTE: If we don't return reasonable values here then the video
|
||||
* unit can potential shut off and won't display an image until re-enabled.
|
||||
* Seems as though the zoom_delta is o.k, and I've not had the problem.
|
||||
* The 'shrink_delta' is prone to this the most - FIXME ! */
|
||||
|
||||
if (*src_w >= *dst_w) {
|
||||
*src_w &= ~0x3;
|
||||
*dst_w &= ~0x3;
|
||||
*shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0;
|
||||
*zoom_delta = 1<<16;
|
||||
if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 )
|
||||
*shrink_delta += 0x10;
|
||||
} else {
|
||||
*src_w &= ~0x3;
|
||||
*dst_w &= ~0x3;
|
||||
*zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0;
|
||||
*shrink_delta = 1<<16;
|
||||
if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 )
|
||||
*zoom_delta += 0x10;
|
||||
}
|
||||
}
|
||||
|
||||
static int frames[VID_PLAY_MAXFRAMES];
|
||||
|
||||
static long overlay_mode, overlay_control;
|
||||
|
||||
int vixConfigPlayback(vidix_playback_t *info)
|
||||
{
|
||||
int shrink, zoom;
|
||||
short src_w, drw_w;
|
||||
short src_h, drw_h;
|
||||
long base0;
|
||||
int pitch;
|
||||
int format;
|
||||
unsigned int i;
|
||||
|
||||
TRACE_ENTER();
|
||||
|
||||
if(!is_supported_fourcc(info->fourcc))
|
||||
return -1;
|
||||
|
||||
switch(info->fourcc){
|
||||
case IMGFMT_YUY2:
|
||||
format = FORMAT_YUV422;
|
||||
break;
|
||||
case IMGFMT_UYVY:
|
||||
format = FORMAT_VUY422;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
src_w = info->src.w;
|
||||
src_h = info->src.h;
|
||||
|
||||
drw_w = info->dest.w;
|
||||
drw_h = info->dest.h;
|
||||
|
||||
pitch = src_w;
|
||||
|
||||
/* Assume we have 16 MB to play with */
|
||||
info->num_frames = 0x1000000 / (pitch * src_h * 2);
|
||||
if(info->num_frames > VID_PLAY_MAXFRAMES)
|
||||
info->num_frames = VID_PLAY_MAXFRAMES;
|
||||
|
||||
/* Start at 16 MB. Let's hope it's not in use. */
|
||||
base0 = 0x1000000;
|
||||
info->dga_addr = pm3_mem + base0;
|
||||
|
||||
info->dest.pitch.y = 2;
|
||||
info->dest.pitch.u = 0;
|
||||
info->dest.pitch.v = 0;
|
||||
info->offset.y = 0;
|
||||
info->offset.v = 0;
|
||||
info->offset.u = 0;
|
||||
info->frame_size = pitch * src_h * 2;
|
||||
for(i = 0; i < info->num_frames; i++){
|
||||
info->offsets[i] = info->frame_size * i;
|
||||
frames[i] = (base0 + info->offsets[i]) >> 1;
|
||||
}
|
||||
|
||||
compute_scale_factor(&src_w, &drw_w, &shrink, &zoom);
|
||||
|
||||
WRITE_REG(PM3VideoOverlayBase0, base0 >> 1);
|
||||
WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch));
|
||||
WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w));
|
||||
WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h));
|
||||
WRITE_REG(PM3VideoOverlayOrigin, 0);
|
||||
|
||||
/* Scale the source to the destinationsize */
|
||||
if (src_h == drw_h) {
|
||||
WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE);
|
||||
} else {
|
||||
WRITE_REG(PM3VideoOverlayYDelta,
|
||||
PM3VideoOverlayYDelta_DELTA(src_h, drw_h));
|
||||
}
|
||||
if (src_w == drw_w) {
|
||||
WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16);
|
||||
WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16);
|
||||
} else {
|
||||
WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink);
|
||||
WRITE_REG(PM3VideoOverlayZoomXDelta, zoom);
|
||||
}
|
||||
WRITE_REG(PM3VideoOverlayIndex, 0);
|
||||
|
||||
/* Now set the ramdac video overlay region and mode */
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (info->dest.x & 0xff));
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (info->dest.x & 0xf00)>>8);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (info->dest.x+drw_w) & 0xff);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh,
|
||||
((info->dest.x+drw_w) & 0xf00)>>8);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (info->dest.y & 0xff));
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (info->dest.y & 0xf00)>>8);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (info->dest.y+drw_h) & 0xff);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh,
|
||||
((info->dest.y+drw_h) & 0xf00)>>8);
|
||||
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0xff);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x00);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xff);
|
||||
|
||||
overlay_mode =
|
||||
1 << 5 |
|
||||
format |
|
||||
PM3VideoOverlayMode_FILTER_FULL |
|
||||
PM3VideoOverlayMode_BUFFERSYNC_MANUAL |
|
||||
PM3VideoOverlayMode_FLIP_VIDEO;
|
||||
|
||||
overlay_control =
|
||||
PM3RD_VideoOverlayControl_KEY_COLOR |
|
||||
PM3RD_VideoOverlayControl_MODE_MAINKEY |
|
||||
PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED;
|
||||
|
||||
TRACE_EXIT();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackOn(void)
|
||||
{
|
||||
TRACE_ENTER();
|
||||
|
||||
WRITE_REG(PM3VideoOverlayMode,
|
||||
overlay_mode | PM3VideoOverlayMode_ENABLE);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayControl,
|
||||
overlay_control | PM3RD_VideoOverlayControl_ENABLE);
|
||||
WRITE_REG(PM3VideoOverlayUpdate,
|
||||
PM3VideoOverlayUpdate_ENABLE);
|
||||
|
||||
TRACE_EXIT();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackOff(void)
|
||||
{
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayControl,
|
||||
PM3RD_VideoOverlayControl_DISABLE);
|
||||
WRITE_REG(PM3VideoOverlayMode,
|
||||
PM3VideoOverlayMode_DISABLE);
|
||||
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0x01);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x01);
|
||||
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xfe);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vixPlaybackFrameSelect(unsigned int frame)
|
||||
{
|
||||
WRITE_REG(PM3VideoOverlayBase0, frames[frame]);
|
||||
return 0;
|
||||
}
|
||||
@ -63,6 +63,15 @@
|
||||
#define CONFIG_CNTL 0x00E0
|
||||
/* CONFIG_CNTL bit constants */
|
||||
# define CFG_VGA_RAM_EN 0x00000100
|
||||
#ifdef RAGE128
|
||||
#define GEN_RESET_CNTL 0x00f0
|
||||
# define SOFT_RESET_GUI 0x00000001
|
||||
# define SOFT_RESET_VCLK 0x00000100
|
||||
# define SOFT_RESET_PCLK 0x00000200
|
||||
# define SOFT_RESET_ECP 0x00000400
|
||||
# define SOFT_RESET_DISPENG_XCLK 0x00000800
|
||||
# define SOFT_RESET_MEMCTLR_XCLK 0x00001000
|
||||
#endif
|
||||
#define CONFIG_MEMSIZE 0x00F8
|
||||
#define CONFIG_APER_0_BASE 0x0100
|
||||
#define CONFIG_APER_1_BASE 0x0104
|
||||
@ -85,7 +94,7 @@
|
||||
#define AMCGPIO_EN_REG 0x01a8
|
||||
#define AMCGPIO_MASK 0x0194
|
||||
#define AMCGPIO_Y_REG 0x01a4
|
||||
#define BM_STATUS 0x0160
|
||||
/*#define BM_STATUS 0x0160*/
|
||||
#define MPP_TB_CONFIG 0x01c0 /* ? */
|
||||
#define MPP_GP_CONFIG 0x01c8 /* ? */
|
||||
#define VENDOR_ID 0x0F00
|
||||
@ -200,10 +209,21 @@
|
||||
#define MEM_INIT_LATENCY_TIMER 0x0154
|
||||
#define MEM_SDRAM_MODE_REG 0x0158
|
||||
#define AGP_BASE 0x0170
|
||||
#ifdef RAGE128
|
||||
#define PCI_GART_PAGE 0x017c
|
||||
#define PC_NGUI_MODE 0x0180
|
||||
#define PC_NGUI_CTLSTAT 0x0184
|
||||
# define PC_FLUSH_GUI (3 << 0)
|
||||
# define PC_RI_GUI (1 << 2)
|
||||
# define PC_FLUSH_ALL 0x00ff
|
||||
# define PC_BUSY (1 << 31)
|
||||
#define PC_MISC_CNTL 0x0188
|
||||
#else
|
||||
#define MEM_IO_CNTL_A1 0x017C
|
||||
#define MEM_IO_CNTL_B0 0x0180
|
||||
#define MEM_IO_CNTL_B1 0x0184
|
||||
#define MC_DEBUG 0x0188
|
||||
#endif
|
||||
#define MC_STATUS 0x0150
|
||||
#define MEM_IO_OE_CNTL 0x018C
|
||||
#define MC_FB_LOCATION 0x0148
|
||||
@ -554,7 +574,9 @@
|
||||
# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */
|
||||
# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */
|
||||
# define SCALER_DIS_LIMIT 0x08000000L
|
||||
#ifdef RAGE128
|
||||
# define SCALER_PRG_LOAD_START 0x10000000L
|
||||
#endif
|
||||
# define SCALER_INT_EMU 0x20000000L
|
||||
# define SCALER_ENABLE 0x40000000L
|
||||
# define SCALER_SOFT_RESET 0x80000000L
|
||||
@ -686,6 +708,18 @@
|
||||
#define OV0_GRAPHICS_KEY_CLR 0x04EC
|
||||
#define OV0_GRAPHICS_KEY_MSK 0x04F0
|
||||
#define OV0_KEY_CNTL 0x04F4
|
||||
#ifdef RAGE128
|
||||
# define VIDEO_KEY_FN_MASK 0x00000007L
|
||||
# define VIDEO_KEY_FN_FALSE 0x00000000L
|
||||
# define VIDEO_KEY_FN_TRUE 0x00000001L
|
||||
# define VIDEO_KEY_FN_EQ 0x00000004L
|
||||
# define VIDEO_KEY_FN_NE 0x00000005L
|
||||
# define GRAPHIC_KEY_FN_MASK 0x00000070L
|
||||
# define GRAPHIC_KEY_FN_FALSE 0x00000000L
|
||||
# define GRAPHIC_KEY_FN_TRUE 0x00000010L
|
||||
# define GRAPHIC_KEY_FN_EQ 0x00000040L
|
||||
# define GRAPHIC_KEY_FN_NE 0x00000050L
|
||||
#else
|
||||
# define VIDEO_KEY_FN_MASK 0x00000003L
|
||||
# define VIDEO_KEY_FN_FALSE 0x00000000L
|
||||
# define VIDEO_KEY_FN_TRUE 0x00000001L
|
||||
@ -696,6 +730,7 @@
|
||||
# define GRAPHIC_KEY_FN_TRUE 0x00000010L
|
||||
# define GRAPHIC_KEY_FN_EQ 0x00000020L
|
||||
# define GRAPHIC_KEY_FN_NE 0x00000030L
|
||||
#endif
|
||||
# define CMP_MIX_MASK 0x00000100L
|
||||
# define CMP_MIX_OR 0x00000000L
|
||||
# define CMP_MIX_AND 0x00000100L
|
||||
@ -783,6 +818,9 @@
|
||||
#define SCRATCH_UMSK 0x0770
|
||||
#define SCRATCH_ADDR 0x0774
|
||||
#define DMA_GUI_TABLE_ADDR 0x0780
|
||||
# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff
|
||||
# define DMA_GUI_COMMAND__INTDIS 0x40000000
|
||||
# define DMA_GUI_COMMAND__EOL 0x80000000
|
||||
#define DMA_GUI_SRC_ADDR 0x0784
|
||||
#define DMA_GUI_DST_ADDR 0x0788
|
||||
#define DMA_GUI_COMMAND 0x078C
|
||||
@ -990,6 +1028,11 @@
|
||||
#define DST_Y_X 0x1438
|
||||
#define DST_WIDTH_HEIGHT 0x1598
|
||||
#define DST_HEIGHT_WIDTH 0x143c
|
||||
#ifdef RAGE128
|
||||
#define GUI_STAT 0x1740
|
||||
# define GUI_FIFOCNT_MASK 0x0fff
|
||||
# define GUI_ACTIVE (1 << 31)
|
||||
#endif
|
||||
#define SRC_CLUT_ADDRESS 0x1780
|
||||
#define SRC_CLUT_DATA 0x1784
|
||||
#define SRC_CLUT_DATA_RD 0x1788
|
||||
@ -1195,13 +1238,29 @@
|
||||
#define PPLL_DIV_2 0x0006
|
||||
#define PPLL_DIV_3 0x0007
|
||||
#define VCLK_ECP_CNTL 0x0008
|
||||
# define VCLK_SRC_SEL_MASK 0x03
|
||||
# define VCLK_SRC_SEL_CPUCLK 0x00
|
||||
# define VCLK_SRC_SEL_PSCANCLK 0x01
|
||||
# define VCLK_SRC_SEL_BYTECLK 0x02
|
||||
# define VCLK_SRC_SEL_PPLLCLK 0x03
|
||||
#define HTOTAL_CNTL 0x0009
|
||||
#define HTOTAL2_CNTL 0x002e /* PLL */
|
||||
#define M_SPLL_REF_FB_DIV 0x000a
|
||||
#define AGP_PLL_CNTL 0x000b
|
||||
#define SPLL_CNTL 0x000c
|
||||
#define SCLK_CNTL 0x000d
|
||||
# define DYN_STOP_LAT_MASK 0x00007ff8
|
||||
# define CP_MAX_DYN_STOP_LAT 0x0008
|
||||
# define SCLK_FORCEON_MASK 0xffff8000
|
||||
#define SCLK_MORE_CNTL 0x0035 /* PLL */
|
||||
# define SCLK_MORE_FORCEON 0x0700
|
||||
#define MPLL_CNTL 0x000e
|
||||
#ifdef RAGE128
|
||||
#define MCLK_CNTL 0x000f /* PLL */
|
||||
# define FORCE_GCP (1 << 16)
|
||||
# define FORCE_PIPE3D_CP (1 << 17)
|
||||
# define FORCE_RCP (1 << 18)
|
||||
#else
|
||||
#define MCLK_CNTL 0x0012
|
||||
/* MCLK_CNTL bit constants */
|
||||
# define FORCEON_MCLKA (1 << 16)
|
||||
@ -1210,6 +1269,7 @@
|
||||
# define FORCEON_YCLKB (1 << 19)
|
||||
# define FORCEON_MC (1 << 20)
|
||||
# define FORCEON_AIC (1 << 21)
|
||||
#endif
|
||||
#define PLL_TEST_CNTL 0x0013
|
||||
#define P2PLL_CNTL 0x002a /* P2PLL */
|
||||
# define P2PLL_RESET (1 << 0)
|
||||
@ -1224,6 +1284,12 @@
|
||||
# define P2PLL_REF_DIV_MASK 0x03ff
|
||||
# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
|
||||
# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
|
||||
#define PIXCLKS_CNTL 0x002d
|
||||
# define PIX2CLK_SRC_SEL_MASK 0x03
|
||||
# define PIX2CLK_SRC_SEL_CPUCLK 0x00
|
||||
# define PIX2CLK_SRC_SEL_PSCANCLK 0x01
|
||||
# define PIX2CLK_SRC_SEL_BYTECLK 0x02
|
||||
# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
|
||||
|
||||
/* masks */
|
||||
|
||||
@ -1236,15 +1302,43 @@
|
||||
#define PPLL_FB3_DIV_MASK 0x000007ff
|
||||
#define PPLL_POST3_DIV_MASK 0x00070000
|
||||
|
||||
#define GUI_ACTIVE 0x80000000
|
||||
/* BUS MASTERING */
|
||||
#define BM_FRAME_BUF_OFFSET 0xA00
|
||||
#define BM_SYSTEM_MEM_ADDR 0xA04
|
||||
#define BM_COMMAND 0xA08
|
||||
# define BM_INTERRUPT_DIS 0x08000000
|
||||
# define BM_TRANSFER_DEST_REG 0x10000000
|
||||
# define BM_FORCE_TO_PCI 0x20000000
|
||||
# define BM_FRAME_OFFSET_HOLD 0x40000000
|
||||
# define BM_END_OF_LIST 0x80000000
|
||||
#define BM_STATUS 0xA0c
|
||||
#define BM_QUEUE_STATUS 0xA10
|
||||
#define BM_QUEUE_FREE_STATUS 0xA14
|
||||
#define BM_CHUNK_0_VAL 0xA18
|
||||
# define BM_PTR_FORCE_TO_PCI 0x00200000
|
||||
# define BM_PM4_RD_FORCE_TO_PCI 0x00400000
|
||||
# define BM_GLOBAL_FORCE_TO_PCI 0x00800000
|
||||
# define BM_VIP3_NOCHUNK 0x10000000
|
||||
# define BM_VIP2_NOCHUNK 0x20000000
|
||||
# define BM_VIP1_NOCHUNK 0x40000000
|
||||
# define BM_VIP0_NOCHUNK 0x80000000
|
||||
#define BM_CHUNK_1_VAL 0xA1C
|
||||
#define BM_VIP0_BUF 0xA20
|
||||
# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0
|
||||
# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1
|
||||
#define BM_VIP0_ACTIVE 0xA24
|
||||
#define BM_VIP1_BUF 0xA30
|
||||
#define BM_VIP1_ACTIVE 0xA34
|
||||
#define BM_VIP2_BUF 0xA40
|
||||
#define BM_VIP2_ACTIVE 0xA44
|
||||
#define BM_VIP3_BUF 0xA50
|
||||
#define BM_VIP3_ACTIVE 0xA54
|
||||
#define BM_VIDCAP_BUF0 0xA60
|
||||
#define BM_VIDCAP_BUF1 0xA64
|
||||
#define BM_VIDCAP_BUF2 0xA68
|
||||
#define BM_VIDCAP_ACTIVE 0xA6c
|
||||
#define BM_GUI 0xA80
|
||||
|
||||
/* GEN_RESET_CNTL bit constants */
|
||||
#define SOFT_RESET_GUI 0x00000001
|
||||
#define SOFT_RESET_VCLK 0x00000100
|
||||
#define SOFT_RESET_PCLK 0x00000200
|
||||
#define SOFT_RESET_ECP 0x00000400
|
||||
#define SOFT_RESET_DISPENG_XCLK 0x00000800
|
||||
|
||||
/* RAGE THEATER REGISTERS */
|
||||
|
||||
#define DMA_VIPH0_COMMAND 0x0A00
|
||||
|
||||
@ -280,6 +280,49 @@ static void radeon_wait_vsync(void)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RAGE128
|
||||
static void _radeon_engine_idle(void);
|
||||
static void _radeon_fifo_wait(unsigned);
|
||||
#define radeon_engine_idle() _radeon_engine_idle()
|
||||
#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries)
|
||||
/* Flush all dirty data in the Pixel Cache to memory. */
|
||||
static __inline__ void radeon_engine_flush ( void )
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL);
|
||||
for (i = 0; i < 2000000; i++) {
|
||||
if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset graphics card to known state. */
|
||||
static void radeon_engine_reset( void )
|
||||
{
|
||||
uint32_t clock_cntl_index;
|
||||
uint32_t mclk_cntl;
|
||||
uint32_t gen_reset_cntl;
|
||||
|
||||
radeon_engine_flush();
|
||||
|
||||
clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
||||
mclk_cntl = INPLL(MCLK_CNTL);
|
||||
|
||||
OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP);
|
||||
|
||||
gen_reset_cntl = INREG(GEN_RESET_CNTL);
|
||||
|
||||
OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
|
||||
INREG(GEN_RESET_CNTL);
|
||||
OUTREG(GEN_RESET_CNTL,
|
||||
gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI));
|
||||
INREG(GEN_RESET_CNTL);
|
||||
|
||||
OUTPLL(MCLK_CNTL, mclk_cntl);
|
||||
OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
||||
OUTREG(GEN_RESET_CNTL, gen_reset_cntl);
|
||||
}
|
||||
#else
|
||||
|
||||
static __inline__ void radeon_engine_flush ( void )
|
||||
{
|
||||
@ -345,9 +388,10 @@ static void radeon_engine_reset( void )
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
static void radeon_engine_restore( void )
|
||||
{
|
||||
#ifndef RAGE128
|
||||
int pitch64;
|
||||
uint32_t xres,yres,bpp;
|
||||
radeon_fifo_wait(1);
|
||||
@ -389,11 +433,45 @@ static void radeon_engine_restore( void )
|
||||
OUTREG(DP_WRITE_MASK, 0xffffffff);
|
||||
|
||||
radeon_engine_idle();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RAGE128
|
||||
static void _radeon_fifo_wait (unsigned entries)
|
||||
{
|
||||
int i;
|
||||
unsigned i;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
for (i=0; i<2000000; i++)
|
||||
if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries)
|
||||
return;
|
||||
radeon_engine_reset();
|
||||
radeon_engine_restore();
|
||||
}
|
||||
}
|
||||
|
||||
static void _radeon_engine_idle ( void )
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
/* ensure FIFO is empty before waiting for idle */
|
||||
radeon_fifo_wait (64);
|
||||
for(;;)
|
||||
{
|
||||
for (i=0; i<2000000; i++) {
|
||||
if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) {
|
||||
radeon_engine_flush ();
|
||||
return;
|
||||
}
|
||||
}
|
||||
radeon_engine_reset();
|
||||
radeon_engine_restore();
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void _radeon_fifo_wait (unsigned entries)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
@ -404,7 +482,6 @@ static void _radeon_fifo_wait (unsigned entries)
|
||||
radeon_engine_restore();
|
||||
}
|
||||
}
|
||||
|
||||
static void _radeon_engine_idle ( void )
|
||||
{
|
||||
int i;
|
||||
@ -414,7 +491,7 @@ static void _radeon_engine_idle ( void )
|
||||
for(;;)
|
||||
{
|
||||
for (i=0; i<2000000; i++) {
|
||||
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
|
||||
if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) {
|
||||
radeon_engine_flush ();
|
||||
return;
|
||||
}
|
||||
@ -423,8 +500,7 @@ static void _radeon_engine_idle ( void )
|
||||
radeon_engine_restore();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef RAGE128
|
||||
/* Reference color space transform data */
|
||||
@ -1064,6 +1140,10 @@ static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
|
||||
if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
|
||||
else pitch = 32;
|
||||
break;
|
||||
case IMGFMT_YVU9:
|
||||
if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy;
|
||||
else pitch = 64;
|
||||
break;
|
||||
default:
|
||||
if(spy >= 16) pitch = spy;
|
||||
else pitch = 16;
|
||||
@ -1099,6 +1179,7 @@ static int radeon_vid_init_video( vidix_playback_t *config )
|
||||
mpitch = best_pitch-1;
|
||||
switch(config->fourcc)
|
||||
{
|
||||
case IMGFMT_YVU9:
|
||||
/* 4:2:0 */
|
||||
case IMGFMT_IYUV:
|
||||
case IMGFMT_YV12:
|
||||
@ -1125,11 +1206,10 @@ static int radeon_vid_init_video( vidix_playback_t *config )
|
||||
dest_w = config->dest.w;
|
||||
dest_h = config->dest.h;
|
||||
if(radeon_is_dbl_scan()) dest_h *= 2;
|
||||
else
|
||||
if(radeon_is_interlace()) dest_h /= 2;
|
||||
besr.dest_bpp = radeon_vid_get_dbpp();
|
||||
besr.fourcc = config->fourcc;
|
||||
besr.v_inc = (src_h << 20) / dest_h;
|
||||
if(radeon_is_interlace()) besr.v_inc *= 2;
|
||||
h_inc = (src_w << 12) / dest_w;
|
||||
step_by = 1;
|
||||
while(h_inc >= (2 << 12)) {
|
||||
@ -1236,46 +1316,50 @@ static void radeon_compute_framesize(vidix_playback_t *info)
|
||||
case IMGFMT_YV12:
|
||||
case IMGFMT_IYUV:
|
||||
awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
|
||||
info->frame_size = (awidth*(info->src.h+info->src.h/2)+dbpp-1)/dbpp;
|
||||
info->frame_size = awidth*(info->src.h+info->src.h/2);
|
||||
break;
|
||||
case IMGFMT_RGB32:
|
||||
case IMGFMT_BGR32:
|
||||
awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
|
||||
info->frame_size = ((awidth*info->src.h)+dbpp-1)/dbpp;
|
||||
info->frame_size = awidth*info->src.h;
|
||||
break;
|
||||
/* YUY2 YVYU, RGB15, RGB16 */
|
||||
default:
|
||||
awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
|
||||
info->frame_size = ((awidth*info->src.h)+dbpp-1)/dbpp;
|
||||
info->frame_size = awidth*info->src.h;
|
||||
break;
|
||||
}
|
||||
info->frame_size *= dbpp;
|
||||
}
|
||||
|
||||
int vixConfigPlayback(vidix_playback_t *info)
|
||||
{
|
||||
unsigned rgb_size;
|
||||
unsigned rgb_size,nfr;
|
||||
if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
|
||||
if(info->num_frames>=VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES-1;
|
||||
if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES;
|
||||
if(info->num_frames==1) besr.double_buff=0;
|
||||
else besr.double_buff=1;
|
||||
radeon_compute_framesize(info);
|
||||
|
||||
rgb_size = radeon_get_xres()*radeon_get_yres()*radeon_vid_get_dbpp();
|
||||
for(;info->num_frames>0; info->num_frames--)
|
||||
rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8);
|
||||
nfr = info->num_frames;
|
||||
for(;nfr>0; nfr--)
|
||||
{
|
||||
radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames;
|
||||
radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
|
||||
radeon_overlay_off &= 0xffff0000;
|
||||
if(radeon_overlay_off >= (int)rgb_size ) break;
|
||||
}
|
||||
if(info->num_frames <= 3)
|
||||
for(;info->num_frames>0; info->num_frames--)
|
||||
if(nfr <= 3)
|
||||
{
|
||||
nfr = info->num_frames;
|
||||
for(;nfr>0; nfr--)
|
||||
{
|
||||
radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames;
|
||||
radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
|
||||
radeon_overlay_off &= 0xffff0000;
|
||||
if(radeon_overlay_off > 0) break;
|
||||
}
|
||||
if(info->num_frames <= 0) return EINVAL;
|
||||
}
|
||||
if(nfr <= 0) return EINVAL;
|
||||
info->num_frames = nfr;
|
||||
besr.vid_nbufs = info->num_frames;
|
||||
info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off;
|
||||
radeon_vid_init_video(info);
|
||||
@ -1453,9 +1537,10 @@ static void set_gr_key( void )
|
||||
{
|
||||
if(radeon_grkey.ckey.op == CKEY_TRUE)
|
||||
{
|
||||
int dbpp=radeon_vid_get_dbpp();
|
||||
besr.ckey_on=1;
|
||||
|
||||
switch(radeon_vid_get_dbpp())
|
||||
switch(dbpp)
|
||||
{
|
||||
case 15:
|
||||
besr.graphics_key_clr=
|
||||
@ -1486,8 +1571,13 @@ static void set_gr_key( void )
|
||||
besr.graphics_key_msk=0;
|
||||
besr.graphics_key_clr=0;
|
||||
}
|
||||
besr.graphics_key_msk = besr.graphics_key_clr;
|
||||
#ifdef RAGE128
|
||||
besr.graphics_key_msk=(1<<dbpp)-1;
|
||||
besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND;
|
||||
#else
|
||||
besr.graphics_key_msk=besr.graphics_key_clr;
|
||||
besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user