mirror of
https://github.com/mpv-player/mpv
synced 2024-12-25 16:33:02 +00:00
CRTC2 YUV support (buggy?) by Jiri.Svoboda@seznam.cz
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@2345 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
arpi
parent
16dc387ec2
commit
8537eef51d
@ -1,3 +1,4 @@
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#define CRTC2
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// YUY2 support (see config.format) added by A'rpi/ESP-team
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// double buffering added by A'rpi/ESP-team
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@ -147,6 +148,31 @@ typedef struct bes_registers_s
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} bes_registers_t;
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static bes_registers_t regs;
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#ifdef CRTC2
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typedef struct crtc2_registers_s
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{
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uint32_t c2ctl;
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uint32_t c2datactl;
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uint32_t c2misc;
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uint32_t c2hparam;
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uint32_t c2hsync;
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uint32_t c2offset;
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uint32_t c2pl2startadd0;
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uint32_t c2pl2startadd1;
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uint32_t c2pl3startadd0;
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uint32_t c2pl3startadd1;
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uint32_t c2preload;
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uint32_t c2spicstartadd0;
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uint32_t c2spicstartadd1;
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uint32_t c2startadd0;
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uint32_t c2startadd1;
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uint32_t c2subpiclut;
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uint32_t c2vcount;
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uint32_t c2vparam;
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uint32_t c2vsync;
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} crtc2_registers_t;
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static crtc2_registers_t cregs;
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#endif
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static uint32_t mga_vid_in_use = 0;
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static uint32_t is_g400 = 0;
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static uint32_t vid_src_ready = 0;
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@ -199,6 +225,32 @@ static int mga_irq = -1;
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#define XCOLKEY0GREEN 0x56
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#define XCOLKEY0BLUE 0x57
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#ifdef CRTC2
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/*CRTC2 registers*/
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#define XMISCCTRL 0x1e
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#define C2CTL 0x3c10
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#define C2DATACTL 0x3c4c
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#define C2MISC 0x3c44
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#define C2HPARAM 0x3c14
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#define C2HSYNC 0x3c18
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#define C2OFFSET 0x3c40
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#define C2PL2STARTADD0 0x3c30 // like BESA1CORG
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#define C2PL2STARTADD1 0x3c34 // like BESA2CORG
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#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG
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#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG
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#define C2PRELOAD 0x3c24
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#define C2SPICSTARTADD0 0x3c54
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#define C2SPICSTARTADD1 0x3c58
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#define C2STARTADD0 0x3c28 // like BESA1ORG
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#define C2STARTADD1 0x3c2c // like BESA2ORG
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#define C2SUBPICLUT 0x3c50
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#define C2VCOUNT 0x3c48
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#define C2VPARAM 0x3c1c
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#define C2VSYNC 0x3c20
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#endif
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// Backend Scaler registers
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#define BESCTL 0x3d20
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#define BESGLOBCTL 0x3dc0
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@ -242,6 +294,37 @@ static int mga_irq = -1;
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static int mga_next_frame=0;
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#ifdef CRTC2
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static void crtc2_frame_sel(int frame)
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{
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switch(frame) {
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case 0:
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cregs.c2pl2startadd0=regs.besa1corg;
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cregs.c2pl3startadd0=regs.besa1c3org;
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cregs.c2startadd0=regs.besa1org;
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break;
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case 1:
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cregs.c2pl2startadd0=regs.besa2corg;
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cregs.c2pl3startadd0=regs.besa2c3org;
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cregs.c2startadd0=regs.besa2org;
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break;
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case 2:
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cregs.c2pl2startadd0=regs.besb1corg;
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cregs.c2pl3startadd0=regs.besb1c3org;
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cregs.c2startadd0=regs.besb1org;
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break;
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case 3:
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cregs.c2pl2startadd0=regs.besb2corg;
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cregs.c2pl3startadd0=regs.besb2c3org;
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cregs.c2startadd0=regs.besb2org;
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break;
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}
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writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
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writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
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writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
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}
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#endif
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static void mga_vid_frame_sel(int frame)
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{
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if ( mga_irq != -1 ) {
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@ -256,6 +339,9 @@ static void mga_vid_frame_sel(int frame)
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// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
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mga_mmio_base + BESGLOBCTL);
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#ifdef CRTC2
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crtc2_frame_sel(frame);
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#endif
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}
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}
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@ -439,6 +525,47 @@ if(!restore){
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printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n",
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readl(mga_mmio_base + BESSTATUS));
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#endif
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#ifdef CRTC2
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// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
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// printk("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC));
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// printk("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl);
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// writel(cregs.c2ctl, mga_mmio_base + C2CTL);
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writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL);
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writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL);
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// ctrc2
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// disable CRTC2 acording to specs
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// writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL);
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// je to treba ???
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// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel
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// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL);
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// writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL);
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// writel(cregs.c2datactl, mga_mmio_base + C2DATACTL);
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// writel(cregs.c2hparam, mga_mmio_base + C2HPARAM);
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// writel(cregs.c2hsync, mga_mmio_base + C2HSYNC);
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// writel(cregs.c2vparam, mga_mmio_base + C2VPARAM);
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// writel(cregs.c2vsync, mga_mmio_base + C2VSYNC);
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writel(cregs.c2misc, mga_mmio_base + C2MISC);
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printk("c2offset = %d\n",cregs.c2offset);
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writel(cregs.c2offset, mga_mmio_base + C2OFFSET);
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writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
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// writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1);
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writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
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// writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1);
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writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
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// writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1);
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writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0);
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// writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1);
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// writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT);
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// writel(cregs.c2preload, mga_mmio_base + C2PRELOAD);
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// finaly enable everything
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// writel(cregs.c2ctl, mga_mmio_base + C2CTL);
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// printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
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// printk("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC));
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#endif
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}
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static int mga_vid_set_config(mga_vid_config_t *config)
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@ -446,6 +573,23 @@ static int mga_vid_set_config(mga_vid_config_t *config)
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int x, y, sw, sh, dw, dh;
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int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
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int frame_size=config->frame_size;
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#ifdef CRTC2
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#define right_margin 0
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#define left_margin 18
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#define hsync_len 46
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#define lower_margin 10
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#define vsync_len 4
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#define upper_margin 39
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unsigned int hdispend = (config->src_width + 31) & ~31;
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unsigned int hsyncstart = hdispend + (right_margin & ~7);
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unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
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unsigned int htotal = hsyncend + (left_margin & ~7);
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unsigned int vdispend = config->src_height;
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unsigned int vsyncstart = vdispend + lower_margin;
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unsigned int vsyncend = vsyncstart + vsync_len;
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unsigned int vtotal = vsyncend + upper_margin;
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#endif
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x = config->x_org;
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y = config->y_org;
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sw = config->src_width;
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@ -598,6 +742,224 @@ if(config->format==MGA_VID_FORMAT_YV12
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regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
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regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
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#ifdef CRTC2
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// pridat hlavni registry - tj. casovani ...
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switch(config->format){
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case MGA_VID_FORMAT_YV12:
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case MGA_VID_FORMAT_I420:
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case MGA_VID_FORMAT_IYUV:
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cregs.c2ctl = 1 // CRTC2 enabled
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+ (1<<1) // external clock
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+ (0<<2) // external clock
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+ (1<<3) // pixel clock enable - not needed ???
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+ (0<<4) // high prioryty req
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+ (1<<5) // high prioryty req
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+ (0<<6) // high prioryty req
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+ (1<<8) // high prioryty req max
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+ (0<<9) // high prioryty req max
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+ (0<<10) // high prioryty req max
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+ (0<<20) // CRTC1 to DAC
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+ (1<<21) // 420 mode
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+ (1<<22) // 420 mode
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+ (1<<23) // 420 mode
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+ (0<<24) // single chroma line for 420 mode - need to be corrected
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+ (0<<25) /*/ interlace mode - need to be corrected*/
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+ (0<<26) // field legth polariry
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+ (0<<27) // field identification polariry
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+ (1<<28) // VIDRST detection mode
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+ (0<<29) // VIDRST detection mode
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+ (1<<30) // Horizontal counter preload
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+ (1<<31) // Vertical counter preload
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;
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cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
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+ (1<<1) // Y filter enable
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+ (1<<2) // CbCr filter enable
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+ (0<<3) // subpicture enable (disabled)
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+ (0<<4) // NTSC enable (disabled - PAL)
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+ (0<<5) // C2 static subpicture enable (disabled)
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+ (0<<6) // C2 subpicture offset division (disabled)
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+ (0<<7) // 422 subformat selection !
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/* + (0<<8) // 15 bpp high alpha
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+ (0<<9) // 15 bpp high alpha
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+ (0<<10) // 15 bpp high alpha
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+ (0<<11) // 15 bpp high alpha
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+ (0<<12) // 15 bpp high alpha
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+ (0<<13) // 15 bpp high alpha
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+ (0<<14) // 15 bpp high alpha
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+ (0<<15) // 15 bpp high alpha
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+ (0<<16) // 15 bpp low alpha
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+ (0<<17) // 15 bpp low alpha
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+ (0<<18) // 15 bpp low alpha
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+ (0<<19) // 15 bpp low alpha
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+ (0<<20) // 15 bpp low alpha
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+ (0<<21) // 15 bpp low alpha
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+ (0<<22) // 15 bpp low alpha
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+ (0<<23) // 15 bpp low alpha
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+ (0<<24) // static subpicture key
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+ (0<<25) // static subpicture key
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+ (0<<26) // static subpicture key
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+ (0<<27) // static subpicture key
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+ (0<<28) // static subpicture key
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*/ ;
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break;
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case MGA_VID_FORMAT_YUY2:
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cregs.c2ctl = 1 // CRTC2 enabled
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+ (1<<1) // external clock
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+ (0<<2) // external clock
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+ (1<<3) // pixel clock enable - not needed ???
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+ (0<<4) // high prioryty req - acc to spec
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+ (1<<5) // high prioryty req
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+ (0<<6) // high prioryty req
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// 7 reserved
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+ (1<<8) // high prioryty req max
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+ (0<<9) // high prioryty req max
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+ (0<<10) // high prioryty req max
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// 11-19 reserved
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+ (0<<20) // CRTC1 to DAC
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+ (1<<21) // 422 mode
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+ (0<<22) // 422 mode
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+ (1<<23) // 422 mode
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+ (0<<24) // single chroma line for 420 mode - need to be corrected
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+ (0<<25) /*/ interlace mode - need to be corrected*/
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+ (0<<26) // field legth polariry
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+ (0<<27) // field identification polariry
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+ (1<<28) // VIDRST detection mode
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+ (0<<29) // VIDRST detection mode
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+ (1<<30) // Horizontal counter preload
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+ (1<<31) // Vertical counter preload
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;
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cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
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+ (1<<1) // Y filter enable
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+ (1<<2) // CbCr filter enable
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+ (0<<3) // subpicture enable (disabled)
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+ (0<<4) // NTSC enable (disabled - PAL)
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+ (0<<5) // C2 static subpicture enable (disabled)
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+ (0<<6) // C2 subpicture offset division (disabled)
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+ (0<<7) // 422 subformat selection !
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/* + (0<<8) // 15 bpp high alpha
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+ (0<<9) // 15 bpp high alpha
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+ (0<<10) // 15 bpp high alpha
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+ (0<<11) // 15 bpp high alpha
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+ (0<<12) // 15 bpp high alpha
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+ (0<<13) // 15 bpp high alpha
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+ (0<<14) // 15 bpp high alpha
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+ (0<<15) // 15 bpp high alpha
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+ (0<<16) // 15 bpp low alpha
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+ (0<<17) // 15 bpp low alpha
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+ (0<<18) // 15 bpp low alpha
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+ (0<<19) // 15 bpp low alpha
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+ (0<<20) // 15 bpp low alpha
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+ (0<<21) // 15 bpp low alpha
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+ (0<<22) // 15 bpp low alpha
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+ (0<<23) // 15 bpp low alpha
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+ (0<<24) // static subpicture key
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+ (0<<25) // static subpicture key
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+ (0<<26) // static subpicture key
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+ (0<<27) // static subpicture key
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+ (0<<28) // static subpicture key
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*/ ;
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break;
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case MGA_VID_FORMAT_UYVY:
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cregs.c2ctl = 1 // CRTC2 enabled
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+ (1<<1) // external clock
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+ (0<<2) // external clock
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+ (1<<3) // pixel clock enable - not needed ???
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+ (0<<4) // high prioryty req
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+ (1<<5) // high prioryty req
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+ (0<<6) // high prioryty req
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+ (1<<8) // high prioryty req max
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+ (0<<9) // high prioryty req max
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+ (0<<10) // high prioryty req max
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+ (0<<20) // CRTC1 to DAC
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+ (1<<21) // 422 mode
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+ (0<<22) // 422 mode
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+ (1<<23) // 422 mode
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+ (1<<24) // single chroma line for 420 mode - need to be corrected
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+ (1<<25) /*/ interlace mode - need to be corrected*/
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+ (0<<26) // field legth polariry
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+ (0<<27) // field identification polariry
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+ (1<<28) // VIDRST detection mode
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+ (0<<29) // VIDRST detection mode
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+ (1<<30) // Horizontal counter preload
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+ (1<<31) // Vertical counter preload
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;
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cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
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+ (1<<1) // Y filter enable
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+ (1<<2) // CbCr filter enable
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+ (0<<3) // subpicture enable (disabled)
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+ (0<<4) // NTSC enable (disabled - PAL)
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+ (0<<5) // C2 static subpicture enable (disabled)
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+ (0<<6) // C2 subpicture offset division (disabled)
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+ (1<<7) // 422 subformat selection !
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/* + (0<<8) // 15 bpp high alpha
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+ (0<<9) // 15 bpp high alpha
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+ (0<<10) // 15 bpp high alpha
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+ (0<<11) // 15 bpp high alpha
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+ (0<<12) // 15 bpp high alpha
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+ (0<<13) // 15 bpp high alpha
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+ (0<<14) // 15 bpp high alpha
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+ (0<<15) // 15 bpp high alpha
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+ (0<<16) // 15 bpp low alpha
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+ (0<<17) // 15 bpp low alpha
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+ (0<<18) // 15 bpp low alpha
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+ (0<<19) // 15 bpp low alpha
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+ (0<<20) // 15 bpp low alpha
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+ (0<<21) // 15 bpp low alpha
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+ (0<<22) // 15 bpp low alpha
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+ (0<<23) // 15 bpp low alpha
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+ (0<<24) // static subpicture key
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+ (0<<25) // static subpicture key
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+ (0<<26) // static subpicture key
|
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+ (0<<27) // static subpicture key
|
||||
+ (0<<28) // static subpicture key
|
||||
*/ ;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
|
||||
return -1;
|
||||
}
|
||||
|
||||
cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
|
||||
cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);
|
||||
|
||||
cregs.c2misc=0 // CRTCV2 656 togg f0
|
||||
+(0<<1) // CRTCV2 656 togg f0
|
||||
+(0<<2) // CRTCV2 656 togg f0
|
||||
+(0<<4) // CRTCV2 656 togg f1
|
||||
+(0<<5) // CRTCV2 656 togg f1
|
||||
+(0<<6) // CRTCV2 656 togg f1
|
||||
+(0<<8) // Hsync active high
|
||||
+(0<<9) // Vsync active high
|
||||
// 16-27 c2vlinecomp - nevim co tam dat
|
||||
;
|
||||
cregs.c2offset=(regs.bespitch << 1);
|
||||
|
||||
cregs.c2pl2startadd0=regs.besa1corg;
|
||||
// cregs.c2pl2startadd1=regs.besa2corg;
|
||||
cregs.c2pl3startadd0=regs.besa1c3org;
|
||||
// cregs.c2pl3startadd1=regs.besa2c3org;
|
||||
|
||||
cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
|
||||
|
||||
cregs.c2spicstartadd0=0; // not used
|
||||
// cregs.c2spicstartadd1=0; // not used
|
||||
|
||||
cregs.c2startadd0=regs.besa1org;
|
||||
// cregs.c2startadd1=regs.besa2org;
|
||||
|
||||
cregs.c2subpiclut=0; //not used
|
||||
|
||||
cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
|
||||
cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
mga_vid_write_regs(0);
|
||||
return 0;
|
||||
}
|
||||
@ -667,6 +1029,11 @@ void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) {
|
||||
// frame=(frame+1)&1;
|
||||
regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
|
||||
writel( regs.besctl, mga_mmio_base + BESCTL );
|
||||
|
||||
#ifdef CRTC2
|
||||
// sem pridat vyber obrazku !!!!
|
||||
crtc2_frame_sel(mga_next_frame);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
++counter;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user