mirror of https://github.com/mpv-player/mpv
Radeon specific gamma correction initialization. (from gatos.sf.net)
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3901 b3059339-0415-0410-9bf9-f77b7e298cf2
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nick
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3f6a5b380c
commit
6b232ba335
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@ -558,7 +558,7 @@
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# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */
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# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */
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# define SCALER_ADAPTIVE_DEINT 0x00001000L
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# define SCALER_UNKNOWN_FLAG0 0x00002000L /* ??? */
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# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
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# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */
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# define SCALER_SMART_SWITCH 0x00008000L
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#ifdef RAGE128
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@ -700,6 +700,20 @@
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#define OV0_GAMMA_10_1F 0x0D44
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#define OV0_GAMMA_20_3F 0x0D48
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#define OV0_GAMMA_40_7F 0x0D4C
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/* These registers exist on R200 only */
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#define OV0_GAMMA_80_BF 0x0E00
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#define OV0_GAMMA_C0_FF 0x0E04
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#define OV0_GAMMA_100_13F 0x0E08
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#define OV0_GAMMA_140_17F 0x0E0C
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#define OV0_GAMMA_180_1BF 0x0E10
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#define OV0_GAMMA_1C0_1FF 0x0E14
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#define OV0_GAMMA_200_23F 0x0E18
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#define OV0_GAMMA_240_27F 0x0E1C
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#define OV0_GAMMA_280_2BF 0x0E20
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#define OV0_GAMMA_2C0_2FF 0x0E24
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#define OV0_GAMMA_300_33F 0x0E28
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#define OV0_GAMMA_340_37F 0x0E2C
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/* End of R200 specific definitions */
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#define OV0_GAMMA_380_3BF 0x0D50
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#define OV0_GAMMA_3C0_3FF 0x0D54
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@ -174,7 +174,9 @@ typedef struct video_registers_s
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}video_registers_t;
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static bes_registers_t besr;
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#ifndef RAGE128
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static int IsR200=0;
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#endif
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#ifdef DEBUG
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#define DECLARE_VREG(name) { #name, name, 0 }
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#else
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@ -455,6 +457,84 @@ static void radeon_vid_dump_regs( void )
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}
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#endif
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#ifndef RAGE128
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/* Gamma curve definition */
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typedef struct
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{
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unsigned int gammaReg;
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unsigned int gammaSlope;
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unsigned int gammaOffset;
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}GAMMA_SETTINGS;
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/* Recommended gamma curve parameters */
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GAMMA_SETTINGS r200_def_gamma[18] =
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{
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{OV0_GAMMA_0_F, 0x100, 0x0000},
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{OV0_GAMMA_10_1F, 0x100, 0x0020},
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{OV0_GAMMA_20_3F, 0x100, 0x0040},
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{OV0_GAMMA_40_7F, 0x100, 0x0080},
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{OV0_GAMMA_80_BF, 0x100, 0x0100},
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{OV0_GAMMA_C0_FF, 0x100, 0x0100},
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{OV0_GAMMA_100_13F, 0x100, 0x0200},
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{OV0_GAMMA_140_17F, 0x100, 0x0200},
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{OV0_GAMMA_180_1BF, 0x100, 0x0300},
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{OV0_GAMMA_1C0_1FF, 0x100, 0x0300},
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{OV0_GAMMA_200_23F, 0x100, 0x0400},
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{OV0_GAMMA_240_27F, 0x100, 0x0400},
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{OV0_GAMMA_280_2BF, 0x100, 0x0500},
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{OV0_GAMMA_2C0_2FF, 0x100, 0x0500},
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{OV0_GAMMA_300_33F, 0x100, 0x0600},
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{OV0_GAMMA_340_37F, 0x100, 0x0600},
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{OV0_GAMMA_380_3BF, 0x100, 0x0700},
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{OV0_GAMMA_3C0_3FF, 0x100, 0x0700}
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};
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GAMMA_SETTINGS r100_def_gamma[6] =
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{
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{OV0_GAMMA_0_F, 0x100, 0x0000},
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{OV0_GAMMA_10_1F, 0x100, 0x0020},
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{OV0_GAMMA_20_3F, 0x100, 0x0040},
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{OV0_GAMMA_40_7F, 0x100, 0x0080},
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{OV0_GAMMA_380_3BF, 0x100, 0x0100},
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{OV0_GAMMA_3C0_3FF, 0x100, 0x0100}
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};
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static void make_default_gamma_correction( void )
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{
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size_t i;
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if(!IsR200){
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OUTREG(OV0_LIN_TRANS_A, 0x12A00000);
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OUTREG(OV0_LIN_TRANS_B, 0x199018FE);
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OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0);
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OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B);
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OUTREG(OV0_LIN_TRANS_E, 0x12A02050);
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OUTREG(OV0_LIN_TRANS_F, 0x0000174E);
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for(i=0; i<6; i++){
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OUTREG(r100_def_gamma[i].gammaReg,
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(r100_def_gamma[i].gammaSlope<<16) |
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r100_def_gamma[i].gammaOffset);
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}
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}
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else{
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OUTREG(OV0_LIN_TRANS_A, 0x12a00000);
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OUTREG(OV0_LIN_TRANS_B, 0x1990190e);
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OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0);
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OUTREG(OV0_LIN_TRANS_D, 0xf3000442);
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OUTREG(OV0_LIN_TRANS_E, 0x12a02040);
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OUTREG(OV0_LIN_TRANS_F, 0x175f);
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/* Default Gamma,
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Of 18 segments for gamma cure, all segments in R200 are programmable,
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while only lower 4 and upper 2 segments are programmable in Radeon*/
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for(i=0; i<18; i++){
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OUTREG(r200_def_gamma[i].gammaReg,
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(r200_def_gamma[i].gammaSlope<<16) |
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r200_def_gamma[i].gammaOffset);
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}
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}
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}
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#endif
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static void radeon_vid_stop_video( void )
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{
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radeon_engine_idle();
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@ -764,6 +844,8 @@ static void radeon_vid_make_default(void)
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{
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#ifdef RAGE128
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OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */
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#else
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make_default_gamma_correction();
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#endif
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besr.deinterlace_pattern = 0x900AAAAA;
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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@ -982,7 +1064,10 @@ static int __init radeon_vid_config_card(void)
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radeon_ram_size /= 0x100000;
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detected_chip = i;
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printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size);
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#ifndef RAGE128
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if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL ||
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ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1;
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#endif
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return TRUE;
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}
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