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Radeon specific gamma correction initialization. (from gatos.sf.net)

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git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3901 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick 2001-12-30 17:28:09 +00:00
parent 3f6a5b380c
commit 6b232ba335
2 changed files with 102 additions and 3 deletions
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16
drivers/radeon/radeon.h
View File

@ -558,7 +558,7 @@
# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */
# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */
# define SCALER_ADAPTIVE_DEINT 0x00001000L
# define SCALER_UNKNOWN_FLAG0 0x00002000L /* ??? */
# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */
# define SCALER_SMART_SWITCH 0x00008000L
#ifdef RAGE128
@ -700,6 +700,20 @@
#define OV0_GAMMA_10_1F 0x0D44
#define OV0_GAMMA_20_3F 0x0D48
#define OV0_GAMMA_40_7F 0x0D4C
/* These registers exist on R200 only */
#define OV0_GAMMA_80_BF 0x0E00
#define OV0_GAMMA_C0_FF 0x0E04
#define OV0_GAMMA_100_13F 0x0E08
#define OV0_GAMMA_140_17F 0x0E0C
#define OV0_GAMMA_180_1BF 0x0E10
#define OV0_GAMMA_1C0_1FF 0x0E14
#define OV0_GAMMA_200_23F 0x0E18
#define OV0_GAMMA_240_27F 0x0E1C
#define OV0_GAMMA_280_2BF 0x0E20
#define OV0_GAMMA_2C0_2FF 0x0E24
#define OV0_GAMMA_300_33F 0x0E28
#define OV0_GAMMA_340_37F 0x0E2C
/* End of R200 specific definitions */
#define OV0_GAMMA_380_3BF 0x0D50
#define OV0_GAMMA_3C0_3FF 0x0D54

89
drivers/radeon/radeon_vid.c
View File

@ -174,7 +174,9 @@ typedef struct video_registers_s
}video_registers_t;
static bes_registers_t besr;
#ifndef RAGE128
static int IsR200=0;
#endif
#ifdef DEBUG
#define DECLARE_VREG(name) { #name, name, 0 }
#else
@ -455,6 +457,84 @@ static void radeon_vid_dump_regs( void )
}
#endif
#ifndef RAGE128
/* Gamma curve definition */
typedef struct
{
unsigned int gammaReg;
unsigned int gammaSlope;
unsigned int gammaOffset;
}GAMMA_SETTINGS;
/* Recommended gamma curve parameters */
GAMMA_SETTINGS r200_def_gamma[18] =
{
{OV0_GAMMA_0_F, 0x100, 0x0000},
{OV0_GAMMA_10_1F, 0x100, 0x0020},
{OV0_GAMMA_20_3F, 0x100, 0x0040},
{OV0_GAMMA_40_7F, 0x100, 0x0080},
{OV0_GAMMA_80_BF, 0x100, 0x0100},
{OV0_GAMMA_C0_FF, 0x100, 0x0100},
{OV0_GAMMA_100_13F, 0x100, 0x0200},
{OV0_GAMMA_140_17F, 0x100, 0x0200},
{OV0_GAMMA_180_1BF, 0x100, 0x0300},
{OV0_GAMMA_1C0_1FF, 0x100, 0x0300},
{OV0_GAMMA_200_23F, 0x100, 0x0400},
{OV0_GAMMA_240_27F, 0x100, 0x0400},
{OV0_GAMMA_280_2BF, 0x100, 0x0500},
{OV0_GAMMA_2C0_2FF, 0x100, 0x0500},
{OV0_GAMMA_300_33F, 0x100, 0x0600},
{OV0_GAMMA_340_37F, 0x100, 0x0600},
{OV0_GAMMA_380_3BF, 0x100, 0x0700},
{OV0_GAMMA_3C0_3FF, 0x100, 0x0700}
};
GAMMA_SETTINGS r100_def_gamma[6] =
{
{OV0_GAMMA_0_F, 0x100, 0x0000},
{OV0_GAMMA_10_1F, 0x100, 0x0020},
{OV0_GAMMA_20_3F, 0x100, 0x0040},
{OV0_GAMMA_40_7F, 0x100, 0x0080},
{OV0_GAMMA_380_3BF, 0x100, 0x0100},
{OV0_GAMMA_3C0_3FF, 0x100, 0x0100}
};
static void make_default_gamma_correction( void )
{
size_t i;
if(!IsR200){
OUTREG(OV0_LIN_TRANS_A, 0x12A00000);
OUTREG(OV0_LIN_TRANS_B, 0x199018FE);
OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0);
OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B);
OUTREG(OV0_LIN_TRANS_E, 0x12A02050);
OUTREG(OV0_LIN_TRANS_F, 0x0000174E);
for(i=0; i<6; i++){
OUTREG(r100_def_gamma[i].gammaReg,
(r100_def_gamma[i].gammaSlope<<16) |
r100_def_gamma[i].gammaOffset);
}
}
else{
OUTREG(OV0_LIN_TRANS_A, 0x12a00000);
OUTREG(OV0_LIN_TRANS_B, 0x1990190e);
OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0);
OUTREG(OV0_LIN_TRANS_D, 0xf3000442);
OUTREG(OV0_LIN_TRANS_E, 0x12a02040);
OUTREG(OV0_LIN_TRANS_F, 0x175f);
/* Default Gamma,
Of 18 segments for gamma cure, all segments in R200 are programmable,
while only lower 4 and upper 2 segments are programmable in Radeon*/
for(i=0; i<18; i++){
OUTREG(r200_def_gamma[i].gammaReg,
(r200_def_gamma[i].gammaSlope<<16) |
r200_def_gamma[i].gammaOffset);
}
}
}
#endif
static void radeon_vid_stop_video( void )
{
radeon_engine_idle();
@ -764,6 +844,8 @@ static void radeon_vid_make_default(void)
{
#ifdef RAGE128
OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */
#else
make_default_gamma_correction();
#endif
besr.deinterlace_pattern = 0x900AAAAA;
OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
@ -982,7 +1064,10 @@ static int __init radeon_vid_config_card(void)
radeon_ram_size /= 0x100000;
detected_chip = i;
printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size);
#ifndef RAGE128
if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL ||
ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1;
#endif
return TRUE;
}