mirror of https://github.com/mpv-player/mpv
hack to get rage128 working on ppc-g3
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@9045 b3059339-0415-0410-9bf9-f77b7e298cf2
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@ -194,7 +194,8 @@ static video_registers_t vregs[] =
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DECLARE_VREG(IDCT_LEVELS),
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DECLARE_VREG(IDCT_AUTH_CONTROL),
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DECLARE_VREG(IDCT_AUTH),
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DECLARE_VREG(IDCT_CONTROL)
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DECLARE_VREG(IDCT_CONTROL),
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DECLARE_VREG(CONFIG_CNTL)
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};
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static void * radeon_mmio_base = 0;
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@ -207,6 +208,11 @@ static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0;
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static uint32_t SAVED_OV0_VID_KEY_CLR = 0;
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static uint32_t SAVED_OV0_VID_KEY_MSK = 0;
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static uint32_t SAVED_OV0_KEY_CNTL = 0;
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#if defined(RAGE128) && (WORDS_BIGENDIAN)
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static uint32_t SAVED_CONFIG_CNTL = 0;
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#define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0)
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#define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0)
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#endif
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#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
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#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
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@ -426,10 +432,10 @@ static void radeon_engine_restore( void )
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(pitch64 << 22));
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radeon_fifo_wait(1);
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//#if defined(__BIG_ENDIAN)
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#if defined(WORDS_BIGENDIAN)
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OUTREGP(DP_DATATYPE,
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HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
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#ifdef RADEON
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OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
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#endif
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#else
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OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
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#endif
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@ -1060,6 +1066,19 @@ int vixInit( void )
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}
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#endif
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/* XXX: hack, but it works for me (tm) */
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#if defined(RAGE128) && (WORDS_BIGENDIAN)
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/* code from gatos */
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{
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SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL);
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OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL &
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~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP));
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// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL,
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// INREG(CONFIG_CNTL));
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}
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#endif
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if(__verbose > 1) radeon_vid_dump_regs();
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return 0;
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}
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@ -1075,6 +1094,12 @@ void vixDestroy( void )
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OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL);
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printf(RADEON_MSG" Restored overlay colorkey settings\n");
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#if defined(RAGE128) && (WORDS_BIGENDIAN)
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OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL);
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// printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL,
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// INREG(CONFIG_CNTL));
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#endif
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unmap_phys_mem(radeon_mem_base,radeon_ram_size);
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unmap_phys_mem(radeon_mmio_base,0xFFFF);
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}
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