mirror of
https://github.com/mpv-player/mpv
synced 2025-01-28 18:53:02 +00:00
First public release
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@2952 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
961ff92ec0
commit
4ef5393875
@ -14,6 +14,8 @@
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* Also here was used code from CVS of GATOS project and X11 trees.
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*/
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#define RADEON_VID_VERSION "0.9.9"
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/*
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It's entirely possible this major conflicts with something else
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mknod /dev/radeon_vid c 178 0
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@ -64,7 +66,7 @@
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MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>");
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MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons");
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MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION);
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MODULE_LICENSE("GPL");
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@ -153,14 +155,14 @@ static uint32_t radeon_vid_in_use = 0;
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static uint8_t *radeon_mmio_base = 0;
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static uint32_t radeon_mem_base = 0;
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#define RADEON_SRC_BASE 8000000ULL /* this driver uses all video memory */
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#define RADEON_SRC_BASE 0x1000000ULL /* this driver uses all video memory */
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static uint32_t radeon_ram_size = 0;
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//static struct video_window radeon_win;
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static mga_vid_config_t radeon_config;
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#define DEBUG 1
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#undef DEBUG
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#if DEBUG
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#define RTRACE printk
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#else
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@ -212,19 +214,23 @@ static void radeon_vid_display_video( void )
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{
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int bes_flags;
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RTRACE("radeon_vid: OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
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RTRACE("radeon_vid: OV0: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs);
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RTRACE("radeon_vid: OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs);
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RTRACE("radeon_vid: OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
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,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
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RTRACE("radeon_vid: OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n"
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,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end);
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RTRACE("radeon_vid: OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n"
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,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init);
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OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
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while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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/*
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OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAAAAA);
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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*/
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OUTREG(OV0_H_INC, besr.h_inc);
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OUTREG(OV0_STEP_BY, besr.step_by);
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OUTREG(OV0_Y_X_START, besr.y_x_start);
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@ -248,7 +254,7 @@ RTRACE("radeon_vid: OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x
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bes_flags = SCALER_ENABLE |
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SCALER_DOUBLE_BUFFER |
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SCALER_ADAPTIVE_DEINT |
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// SCALER_ADAPTIVE_DEINT |
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SCALER_SMART_SWITCH |
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SCALER_HORZ_PICK_NEAREST;
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switch(besr.fourcc)
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@ -271,6 +277,7 @@ RTRACE("radeon_vid: OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x
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case IMGFMT_YUY2:
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default: bes_flags |= SCALER_SOURCE_VYUY422; break;
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}
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RTRACE("radeon_vid: OV0: SCALER=%x\n",bes_flags);
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OUTREG(OV0_SCALE_CNTL, bes_flags);
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/*
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TODO:
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@ -290,21 +297,22 @@ static void radeon_vid_start_video( void )
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radeon_vid_display_video();
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}
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#define XXX_SRC_X 0
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#define XXX_SRC_Y 0
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#define XXX_SRC_X 0
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#define XXX_SRC_Y 0
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#define XXX_WIDTH config->src_width
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#define XXX_HEIGHT config->src_height
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#define XXX_DRW_W (config->dest_width)
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#define XXX_DRW_H (config->dest_height)
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#define XXX_DRW_W config->dest_width
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#define XXX_DRW_H config->dest_height
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static int radeon_vid_init_video( mga_vid_config_t *config )
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{
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uint32_t tmp,left,src_w,pitch,h_inc,step_by;
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uint32_t tmp,src_w,pitch,h_inc,step_by,left,top;
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RTRACE("radeon_vid: usr_config: version = %x card=%x ram=%x src(%xx%x) dest(%x:%xx%x:%x) frame_size=%x num_frames=%x\n"
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RTRACE("radeon_vid: usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n"
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,(uint32_t)config->version
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,(uint32_t)config->format
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,(uint32_t)config->card_type
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,(uint32_t)config->ram_size
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,(uint32_t)config->src_width
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@ -339,11 +347,32 @@ RTRACE("radeon_vid: usr_config: version = %x card=%x ram=%x src(%xx%x) dest(%x:%
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printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format);
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return -1;
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}
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pitch = ((XXX_WIDTH << 1) + 15) & ~15;
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switch(config->format)
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{
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default:
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case IMGFMT_YVU9:
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case IMGFMT_IYUV:
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case IMGFMT_UYVY:
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case IMGFMT_YV12:
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case IMGFMT_I420:
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case IMGFMT_YUY2:
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case IMGFMT_RGB15:
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case IMGFMT_BGR15:
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case IMGFMT_RGB16:
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case IMGFMT_BGR16: pitch = ((XXX_WIDTH*2) + 15) & ~15; break;
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case IMGFMT_RGB24:
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case IMGFMT_BGR24: pitch = ((XXX_WIDTH*3) + 15) & ~15; break;
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case IMGFMT_RGB32:
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case IMGFMT_BGR32: pitch = ((XXX_WIDTH*4) + 15) & ~15; break;
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}
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/*pitch 9c0 ->4e0 */
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left = XXX_SRC_X << 16;
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top = XXX_SRC_Y << 16;
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besr.fourcc = config->format;
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besr.v_inc = (config->src_height << 20) / XXX_DRW_H;
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besr.v_inc = (config->src_height << 20) / XXX_DRW_H; /*9c0e0 -> 9c528*/
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h_inc = (config->src_width << 12) / XXX_DRW_W;
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step_by = 1;
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@ -355,28 +384,28 @@ RTRACE("radeon_vid: usr_config: version = %x card=%x ram=%x src(%xx%x) dest(%x:%
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/* keep everything in 16.16 */
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besr.vid_buf0_base_adrs = RADEON_SRC_BASE; /* I guess that offset 0 is o'k */
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besr.vid_buf0_base_adrs += (((XXX_SRC_X >> 16) & ~7) << 1)&0xfffffff0;
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besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0;
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besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
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besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs;
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besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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tmp = (XXX_SRC_X & 0x0003ffff) + 0x00028000 + (h_inc << 3);
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tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
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besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
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((tmp << 12) & 0xf0000000);
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((tmp << 12) & 0xf0000000);
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tmp = ((XXX_SRC_X >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
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tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
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besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
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((tmp << 12) & 0x70000000);
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((tmp << 12) & 0x70000000);
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tmp = (XXX_SRC_Y & 0x0000ffff) + 0x00018000;
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tmp = (top & 0x0000ffff) + 0x00018000;
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besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
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left = (XXX_SRC_X >> 16) & 7;
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left = (left >> 16) & 7;
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besr.h_inc = h_inc | ((h_inc >> 1) << 16);
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besr.step_by = step_by | (step_by << 8);
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besr.y_x_start = (config->x_org) | (config->y_org << 16);
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besr.y_x_start = (config->x_org+8) | (config->y_org << 16); /*5c008->5d009*/
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besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16);
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besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16);
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besr.vid_buf_pitch0_value = pitch;
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@ -412,6 +441,8 @@ static void radeon_vid_frame_sel(int frame)
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}
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static int video_on = 0;
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static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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{
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int frame;
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@ -458,11 +489,13 @@ static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int
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case MGA_VID_ON:
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RTRACE( "radeon_vid: Video ON (ioctl)\n");
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radeon_vid_start_video();
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video_on = 1;
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break;
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case MGA_VID_OFF:
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RTRACE( "radeon_vid: Video OFF (ioctl)\n");
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radeon_vid_stop_video();
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if(video_on) radeon_vid_stop_video();
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video_on = 0;
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break;
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case MGA_VID_FSEL:
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@ -52,12 +52,41 @@ uint32_t num_frames;
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#define IMGFMT_BGR24 (IMGFMT_BGR|24)
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#define IMGFMT_BGR32 (IMGFMT_BGR|32)
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#define IMGFMT_YV12 0x32315659
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#define IMGFMT_IYUV (('I'<<24)|('Y'<<16)|('U'<<8)|'V')
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#define IMGFMT_I420 (('I'<<24)|('4'<<16)|('2'<<8)|'0')
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#define IMGFMT_YUY2 (('Y'<<24)|('U'<<16)|('Y'<<8)|'2')
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#define IMGFMT_UYVY (('U'<<24)|('Y'<<16)|('V'<<8)|'Y')
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#define IMGFMT_IS_RGB(fmt) ((fmt&IMGFMT_RGB_MASK)==IMGFMT_RGB)
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#define IMGFMT_IS_BGR(fmt) ((fmt&IMGFMT_BGR_MASK)==IMGFMT_BGR)
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#define IMGFMT_RGB_DEPTH(fmt) (fmt&~IMGFMT_RGB)
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#define IMGFMT_BGR_DEPTH(fmt) (fmt&~IMGFMT_BGR)
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/* Planar YUV Formats */
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#define IMGFMT_YVU9 0x39555659
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#define IMGFMT_IF09 0x39304649
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#define IMGFMT_YV12 0x32315659
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#define IMGFMT_I420 0x30323449
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#define IMGFMT_IYUV 0x56555949
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#define IMGFMT_CLPL 0x4C504C43
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/* Packed YUV Formats */
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#define IMGFMT_IYU1 0x31555949
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#define IMGFMT_IYU2 0x32555949
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#define IMGFMT_UYVY 0x59565955
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#define IMGFMT_UYNV 0x564E5955
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#define IMGFMT_cyuv 0x76757963
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#define IMGFMT_YUY2 0x32595559
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#define IMGFMT_YUNV 0x564E5559
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#define IMGFMT_YVYU 0x55595659
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#define IMGFMT_Y41P 0x50313459
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#define IMGFMT_Y211 0x31313259
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#define IMGFMT_Y41T 0x54313459
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#define IMGFMT_Y42T 0x54323459
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#define IMGFMT_V422 0x32323456
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#define IMGFMT_V655 0x35353656
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#define IMGFMT_CLJR 0x524A4C43
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#define IMGFMT_YUVP 0x50565559
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#define IMGFMT_UYVP 0x50565955
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#define MGA_VID_CONFIG _IOR('J', 1, mga_vid_config_t)
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#define MGA_VID_ON _IO ('J', 2)
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