mirror of https://github.com/mpv-player/mpv
Code cleanup
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3349 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
80c8cc6972
commit
3fb5532a3b
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@ -102,6 +102,13 @@ static int swap_fourcc __initdata = 0;
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#endif
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#endif
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#undef DEBUG
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#if DEBUG
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#define RTRACE printk
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#else
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#define RTRACE(...) ((void)0)
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#endif
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typedef struct bes_registers_s
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{
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/* base address of yuv framebuffer */
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@ -158,71 +165,80 @@ typedef struct bes_registers_s
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typedef struct video_registers_s
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{
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#ifdef DEBUG
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const char * sname;
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#endif
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uint32_t name;
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uint32_t value;
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}video_registers_t;
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static bes_registers_t besr;
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#ifdef DEBUG
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#define DECLARE_VREG(name) { #name, name, 0 }
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#else
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#define DECLARE_VREG(name) { name, 0 }
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#endif
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static video_registers_t vregs[] =
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{
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{ "OV0_Y_X_START", OV0_Y_X_START, 0 },
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{ "OV0_Y_X_END", OV0_Y_X_END, 0 },
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{ "OV0_PIPELINE_CNTL", OV0_PIPELINE_CNTL, 0 },
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{ "OV0_EXCLUSIVE_HORZ", OV0_EXCLUSIVE_HORZ, 0 },
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{ "OV0_EXCLUSIVE_VERT", OV0_EXCLUSIVE_VERT, 0 },
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{ "OV0_REG_LOAD_CNTL", OV0_REG_LOAD_CNTL, 0 },
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{ "OV0_SCALE_CNTL", OV0_SCALE_CNTL, 0 },
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{ "OV0_V_INC", OV0_V_INC, 0 },
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{ "OV0_P1_V_ACCUM_INIT", OV0_P1_V_ACCUM_INIT, 0 },
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{ "OV0_P23_V_ACCUM_INIT", OV0_P23_V_ACCUM_INIT, 0 },
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{ "OV0_P1_BLANK_LINES_AT_TOP", OV0_P1_BLANK_LINES_AT_TOP, 0 },
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{ "OV0_P23_BLANK_LINES_AT_TOP", OV0_P23_BLANK_LINES_AT_TOP, 0 },
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{ "OV0_BASE_ADDR", OV0_BASE_ADDR, 0 },
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{ "OV0_VID_BUF0_BASE_ADRS", OV0_VID_BUF0_BASE_ADRS, 0 },
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{ "OV0_VID_BUF1_BASE_ADRS", OV0_VID_BUF1_BASE_ADRS, 0 },
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{ "OV0_VID_BUF2_BASE_ADRS", OV0_VID_BUF2_BASE_ADRS, 0 },
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{ "OV0_VID_BUF3_BASE_ADRS", OV0_VID_BUF3_BASE_ADRS, 0 },
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{ "OV0_VID_BUF4_BASE_ADRS", OV0_VID_BUF4_BASE_ADRS, 0 },
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{ "OV0_VID_BUF5_BASE_ADRS", OV0_VID_BUF5_BASE_ADRS, 0 },
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{ "OV0_VID_BUF_PITCH0_VALUE", OV0_VID_BUF_PITCH0_VALUE, 0 },
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{ "OV0_VID_BUF_PITCH1_VALUE", OV0_VID_BUF_PITCH1_VALUE, 0 },
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{ "OV0_AUTO_FLIP_CNTL", OV0_AUTO_FLIP_CNTL, 0 },
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{ "OV0_DEINTERLACE_PATTERN", OV0_DEINTERLACE_PATTERN, 0 },
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{ "OV0_SUBMIT_HISTORY", OV0_SUBMIT_HISTORY, 0 },
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{ "OV0_H_INC", OV0_H_INC, 0 },
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{ "OV0_STEP_BY", OV0_STEP_BY, 0 },
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{ "OV0_P1_H_ACCUM_INIT", OV0_P1_H_ACCUM_INIT, 0 },
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{ "OV0_P23_H_ACCUM_INIT", OV0_P23_H_ACCUM_INIT, 0 },
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{ "OV0_P1_X_START_END", OV0_P1_X_START_END, 0 },
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{ "OV0_P2_X_START_END", OV0_P2_X_START_END, 0 },
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{ "OV0_P3_X_START_END", OV0_P3_X_START_END, 0 },
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{ "OV0_FILTER_CNTL", OV0_FILTER_CNTL, 0 },
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{ "OV0_FOUR_TAP_COEF_0", OV0_FOUR_TAP_COEF_0, 0 },
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{ "OV0_FOUR_TAP_COEF_1", OV0_FOUR_TAP_COEF_1, 0 },
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{ "OV0_FOUR_TAP_COEF_2", OV0_FOUR_TAP_COEF_2, 0 },
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{ "OV0_FOUR_TAP_COEF_3", OV0_FOUR_TAP_COEF_3, 0 },
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{ "OV0_FOUR_TAP_COEF_4", OV0_FOUR_TAP_COEF_4, 0 },
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{ "OV0_FLAG_CNTL", OV0_FLAG_CNTL, 0 },
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{ "OV0_COLOUR_CNTL", OV0_COLOUR_CNTL, 0 },
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{ "OV0_VID_KEY_CLR", OV0_VID_KEY_CLR, 0 },
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{ "OV0_VID_KEY_MSK", OV0_VID_KEY_MSK, 0 },
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{ "OV0_GRAPHICS_KEY_CLR", OV0_GRAPHICS_KEY_CLR, 0 },
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{ "OV0_GRAPHICS_KEY_MSK", OV0_GRAPHICS_KEY_MSK, 0 },
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{ "OV0_KEY_CNTL", OV0_KEY_CNTL, 0 },
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{ "OV0_TEST", OV0_TEST, 0 },
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{ "OV0_LIN_TRANS_A", OV0_LIN_TRANS_A, 0 },
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{ "OV0_LIN_TRANS_B", OV0_LIN_TRANS_B, 0 },
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{ "OV0_LIN_TRANS_C", OV0_LIN_TRANS_C, 0 },
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{ "OV0_LIN_TRANS_D", OV0_LIN_TRANS_D, 0 },
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{ "OV0_LIN_TRANS_E", OV0_LIN_TRANS_E, 0 },
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{ "OV0_LIN_TRANS_F", OV0_LIN_TRANS_F, 0 },
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{ "OV0_GAMMA_0_F", OV0_GAMMA_0_F, 0 },
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{ "OV0_GAMMA_10_1F", OV0_GAMMA_10_1F, 0 },
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{ "OV0_GAMMA_20_3F", OV0_GAMMA_20_3F, 0 },
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{ "OV0_GAMMA_40_7F", OV0_GAMMA_40_7F, 0 },
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{ "OV0_GAMMA_380_3BF", OV0_GAMMA_380_3BF, 0 },
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{ "OV0_GAMMA_3C0_3FF", OV0_GAMMA_3C0_3FF, 0 }
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DECLARE_VREG(OV0_Y_X_START),
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DECLARE_VREG(OV0_Y_X_END),
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DECLARE_VREG(OV0_PIPELINE_CNTL),
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DECLARE_VREG(OV0_EXCLUSIVE_HORZ),
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DECLARE_VREG(OV0_EXCLUSIVE_VERT),
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DECLARE_VREG(OV0_REG_LOAD_CNTL),
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DECLARE_VREG(OV0_SCALE_CNTL),
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DECLARE_VREG(OV0_V_INC),
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DECLARE_VREG(OV0_P1_V_ACCUM_INIT),
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DECLARE_VREG(OV0_P23_V_ACCUM_INIT),
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DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP),
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DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP),
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DECLARE_VREG(OV0_BASE_ADDR),
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DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS),
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DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE),
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DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE),
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DECLARE_VREG(OV0_AUTO_FLIP_CNTL),
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DECLARE_VREG(OV0_DEINTERLACE_PATTERN),
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DECLARE_VREG(OV0_SUBMIT_HISTORY),
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DECLARE_VREG(OV0_H_INC),
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DECLARE_VREG(OV0_STEP_BY),
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DECLARE_VREG(OV0_P1_H_ACCUM_INIT),
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DECLARE_VREG(OV0_P23_H_ACCUM_INIT),
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DECLARE_VREG(OV0_P1_X_START_END),
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DECLARE_VREG(OV0_P2_X_START_END),
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DECLARE_VREG(OV0_P3_X_START_END),
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DECLARE_VREG(OV0_FILTER_CNTL),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_0),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_1),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_2),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_3),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_4),
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DECLARE_VREG(OV0_FLAG_CNTL),
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DECLARE_VREG(OV0_COLOUR_CNTL),
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DECLARE_VREG(OV0_VID_KEY_CLR),
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DECLARE_VREG(OV0_VID_KEY_MSK),
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DECLARE_VREG(OV0_GRAPHICS_KEY_CLR),
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DECLARE_VREG(OV0_GRAPHICS_KEY_MSK),
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DECLARE_VREG(OV0_KEY_CNTL),
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DECLARE_VREG(OV0_TEST),
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DECLARE_VREG(OV0_LIN_TRANS_A),
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DECLARE_VREG(OV0_LIN_TRANS_B),
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DECLARE_VREG(OV0_LIN_TRANS_C),
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DECLARE_VREG(OV0_LIN_TRANS_D),
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DECLARE_VREG(OV0_LIN_TRANS_E),
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DECLARE_VREG(OV0_LIN_TRANS_F),
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DECLARE_VREG(OV0_GAMMA_0_F),
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DECLARE_VREG(OV0_GAMMA_10_1F),
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DECLARE_VREG(OV0_GAMMA_20_3F),
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DECLARE_VREG(OV0_GAMMA_40_7F),
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DECLARE_VREG(OV0_GAMMA_380_3BF),
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DECLARE_VREG(OV0_GAMMA_3C0_3FF)
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};
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static uint32_t radeon_vid_in_use = 0;
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@ -237,13 +253,6 @@ static uint32_t radeon_param_buff_size=0;
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static uint32_t radeon_param_buff_len=0; /* real length of buffer */
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static mga_vid_config_t radeon_config;
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#undef DEBUG
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#if DEBUG
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#define RTRACE printk
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#else
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#define RTRACE(...) ((void)0)
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#endif
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static char *fourcc_format_name(int format)
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{
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switch(format)
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@ -301,15 +310,6 @@ static char *fourcc_format_name(int format)
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#define INREG(addr) readl((radeon_mmio_base)+addr)
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#define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr)
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static __inline__ void _radeon_fifo_wait (int entries)
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{
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int i;
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for (i=0; i<2000000; i++)
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if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
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return;
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}
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static uint32_t radeon_vid_get_dbpp( void )
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{
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uint32_t dbpp,retval;
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@ -367,6 +367,8 @@ static void radeon_vid_display_video( void )
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while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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@ -382,9 +384,6 @@ static void radeon_vid_display_video( void )
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}
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else OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE);
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_H_INC, besr.h_inc);
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OUTREG(OV0_STEP_BY, besr.step_by);
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OUTREG(OV0_Y_X_START, besr.y_x_start);
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@ -457,23 +456,6 @@ static void radeon_vid_display_video( void )
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void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B)
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{
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besr.ckey_on = ckey_on;
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switch(radeon_vid_get_dbpp() == 16)
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{
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case 16:
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/* 5.6.5 mode,
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note that these values depend on DAC_CNTL.EXPAND_MODE setting */
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R = (R<<3);
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G = (G<<2);
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B = (B<<3);
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// besr.graphics_key_msk=((R|0x7)<<16)|((G|0x3)<<8)|(B|0x7)|(0xff<<24);
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besr.graphics_key_msk=((R|0x7)<<16)|((G|0x3)<<8)|(B|0x7)|(0xff<<24);
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break;
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case 24: besr.graphics_key_msk = ((R)<<16)|((G)<<8)|(B);
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break;
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case 32:
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default: besr.graphics_key_msk = ((R)<<16)|((G)<<8)|(B)|(0xff<<24);
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break;
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}
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besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1;
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besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24);
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}
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