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git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3474 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick 2001-12-12 18:48:07 +00:00
parent 587bfe43a7
commit 3eba4f11b1
3 changed files with 57 additions and 2 deletions
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28
drivers/radeon/hacking
View File

@ -279,6 +279,34 @@ Please compare:
(is not MMX optimized that's gladly accepted, but probably (is not MMX optimized that's gladly accepted, but probably
will be never optimized due portability). will be never optimized due portability).
hardware IDCT support diagram:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
[ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ]
| | |
[ Variable length decoder] |D |
| |V |
[ Inverse quantization ] |D |
| | |
-------|---[ video card ]---------+ |s |
| | |u |
[ Run level decode & de-zigzag ] | |b |
| | |p |
[ IDCT ] | |i |
| | |c |
[ Motion compensation ] | |t |
| | |u |
[ Advanced deinterlacing ] | |r |
| | |e |
[ Filtered X-Y scaling ] [SUBPIC]-|-----+s [ OSD ]
| | | | |
[ 4-bit alpha blending ] <---+ | +-------+
| |
[ YUV to RGB conversion ] |
-------|--------------------------+
TV-screen or CRT-display
Conslusion: Conslusion:
~~~~~~~~~~~ ~~~~~~~~~~~

1
drivers/radeon/radeon.h
View File

@ -523,7 +523,6 @@
# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L # define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L # define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
# define REG_LD_CTL_LOCK_READBACK 0x00000008L # define REG_LD_CTL_LOCK_READBACK 0x00000008L
/*#define OV0_REG_SLICE_CNTL 0xXXXX*/
#define OV0_SCALE_CNTL 0x0420 #define OV0_SCALE_CNTL 0x0420
# define SCALER_PIX_EXPAND 0x00000001L # define SCALER_PIX_EXPAND 0x00000001L
# define SCALER_Y2R_TEMP 0x00000002L # define SCALER_Y2R_TEMP 0x00000002L

30
drivers/radeon/radeon_vid.c
View File

@ -183,6 +183,11 @@ static bes_registers_t besr;
static video_registers_t vregs[] = static video_registers_t vregs[] =
{ {
DECLARE_VREG(VIDEOMUX_CNTL),
DECLARE_VREG(VIPPAD_MASK),
DECLARE_VREG(VIPPAD1_A),
DECLARE_VREG(VIPPAD1_EN),
DECLARE_VREG(VIPPAD1_Y),
DECLARE_VREG(OV0_Y_X_START), DECLARE_VREG(OV0_Y_X_START),
DECLARE_VREG(OV0_Y_X_END), DECLARE_VREG(OV0_Y_X_END),
DECLARE_VREG(OV0_PIPELINE_CNTL), DECLARE_VREG(OV0_PIPELINE_CNTL),
@ -243,7 +248,30 @@ static video_registers_t vregs[] =
DECLARE_VREG(OV0_GAMMA_20_3F), DECLARE_VREG(OV0_GAMMA_20_3F),
DECLARE_VREG(OV0_GAMMA_40_7F), DECLARE_VREG(OV0_GAMMA_40_7F),
DECLARE_VREG(OV0_GAMMA_380_3BF), DECLARE_VREG(OV0_GAMMA_380_3BF),
DECLARE_VREG(OV0_GAMMA_3C0_3FF) DECLARE_VREG(OV0_GAMMA_3C0_3FF),
DECLARE_VREG(SUBPIC_CNTL),
DECLARE_VREG(SUBPIC_DEFCOLCON),
DECLARE_VREG(SUBPIC_Y_X_START),
DECLARE_VREG(SUBPIC_Y_X_END),
DECLARE_VREG(SUBPIC_V_INC),
DECLARE_VREG(SUBPIC_H_INC),
DECLARE_VREG(SUBPIC_BUF0_OFFSET),
DECLARE_VREG(SUBPIC_BUF1_OFFSET),
DECLARE_VREG(SUBPIC_LC0_OFFSET),
DECLARE_VREG(SUBPIC_LC1_OFFSET),
DECLARE_VREG(SUBPIC_PITCH),
DECLARE_VREG(SUBPIC_BTN_HLI_COLCON),
DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START),
DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END),
DECLARE_VREG(SUBPIC_PALETTE_INDEX),
DECLARE_VREG(SUBPIC_PALETTE_DATA),
DECLARE_VREG(SUBPIC_H_ACCUM_INIT),
DECLARE_VREG(SUBPIC_V_ACCUM_INIT),
DECLARE_VREG(IDCT_RUNS),
DECLARE_VREG(IDCT_LEVELS),
DECLARE_VREG(IDCT_AUTH_CONTROL),
DECLARE_VREG(IDCT_AUTH),
DECLARE_VREG(IDCT_CONTROL)
}; };
static uint32_t radeon_vid_in_use = 0; static uint32_t radeon_vid_in_use = 0;