mirror of https://github.com/mpv-player/mpv
Tuned some registers
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@3471 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick
parent
7e23494f8c
commit
14feef905d
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@ -64,8 +64,11 @@ cat /dev/radeon_vid
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List of parameters:
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~~~~~~~~~~~~~~~~~~~
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if you have rage128 chip:
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brightness=decval (-64:+63) doesn't work on radeons
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saturation=decval (0:+31) doesn't work on radeons
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endif
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double_buff=on/off enables/disables double buffering
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deinterlace=on/off enables/disables adaprive deinterlacing
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deinterlace_pattern=hexval defines deinterlacing pattern
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@ -138,6 +138,14 @@
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# define AGP_4X_MODE 0x04
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# define AGP_MODE_MASK 0x07
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#define AGP_COMMAND 0x0F60
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/* Video muxer unit */
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#define VIDEOMUX_CNTL 0x0190
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#define VIPPAD_MASK 0x0198
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#define VIPPAD1_A 0x01AC
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#define VIPPAD1_EN 0x01B0
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#define VIPPAD1_Y 0x01B4
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#define AIC_CTRL 0x01D0
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#define AIC_STAT 0x01D4
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#define AIC_PT_BASE 0x01D8
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@ -496,7 +504,9 @@
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#define GRPH_BUFFER_CNTL 0x02F0
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#define VGA_BUFFER_CNTL 0x02F4
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/* first overlay unit (there is only one) */
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/* first overlay unit (there is only one) */
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#define OV0_Y_X_START 0x0400
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#define OV0_Y_X_END 0x0404
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#define OV0_PIPELINE_CNTL 0x0408
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@ -642,13 +652,30 @@
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value 0x8 ???
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value 0xffffffff doesn't make any visible effects
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*/
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/*
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Top quality 4x4-tap filtered vertical and horizontal scaler.
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It allows up to 64:1 upscaling and downscaling without
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performance or quality degradation.
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*/
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#define OV0_FOUR_TAP_COEF_0 0x04B0
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#define OV0_FOUR_TAP_COEF_1 0x04B4
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#define OV0_FOUR_TAP_COEF_2 0x04B8
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#define OV0_FOUR_TAP_COEF_3 0x04BC
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#define OV0_FOUR_TAP_COEF_4 0x04C0
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#define OV0_FLAG_CNTL 0x04DC /* probably wronly defined for radeons */
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#define OV0_COLOUR_CNTL 0x04E0 /* probably wronly defined for radeons */
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#define OV0_FLAG_CNTL 0x04DC
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#ifdef RAGE128
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#define OV0_COLOUR_CNTL 0x04E0
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# define COLOUR_CNTL_BRIGHTNESS 0x0000007F
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# define COLOUR_CNTL_SATURATION 0x001F1F00
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#else
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/* NB: radeons have no COLOUR_CNTL register */
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#define OV0_SLICE_CNTL 0x04E0
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# define SLICE_CNTL_DISABLE 0x40000000
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#endif
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/* Video and graphics keys allow alpha blending, color correction
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and many other video effects */
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#define OV0_VID_KEY_CLR 0x04E4
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#define OV0_VID_KEY_MSK 0x04E8
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#define OV0_GRAPHICS_KEY_CLR 0x04EC
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@ -681,8 +708,22 @@
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#define OV0_GAMMA_380_3BF 0x0D50
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#define OV0_GAMMA_3C0_3FF 0x0D54
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/* subpicture unit */
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/*
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IDCT ENGINE:
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It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag
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and IDCT into an IDCT engine to complement the motion compensation engine.
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*/
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#define IDCT_RUNS 0x1F80
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#define IDCT_LEVELS 0x1F84
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#define IDCT_AUTH_CONTROL 0x1F88
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#define IDCT_AUTH 0x1F8C
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#define IDCT_CONTROL 0x1FBC
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/*
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SUBPICTURE UNIT:
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Decompressing, scaling and alpha blending the compressed bitmap on the fly.
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Provide optimal DVD subpicture qualtity.
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*/
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#define SUBPIC_CNTL 0x0540
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#define SUBPIC_DEFCOLCON 0x0544
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#define SUBPIC_Y_X_START 0x054C
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@ -702,6 +743,38 @@
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#define SUBPIC_H_ACCUM_INIT 0x0584
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#define SUBPIC_V_ACCUM_INIT 0x0588
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#define CP_RB_BASE 0x0700
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#define CP_RB_CNTL 0x0704
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#define CP_RB_RPTR_ADDR 0x070C
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#define CP_RB_RPTR 0x0710
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#define CP_RB_WPTR 0x0714
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#define CP_RB_WPTR_DELAY 0x0718
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#define CP_IB_BASE 0x0738
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#define CP_IB_BUFSZ 0x073C
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#define CP_CSQ_CNTL 0x0740
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#define SCRATCH_UMSK 0x0770
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#define SCRATCH_ADDR 0x0774
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#define DMA_GUI_TABLE_ADDR 0x0780
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#define DMA_GUI_SRC_ADDR 0x0784
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#define DMA_GUI_DST_ADDR 0x0788
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#define DMA_GUI_COMMAND 0x078C
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#define DMA_GUI_STATUS 0x0790
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#define DMA_GUI_ACT_DSCRPTR 0x0794
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#define DMA_VID_TABLE_ADDR 0x07A0
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#define DMA_VID_SRC_ADDR 0x07A4
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#define DMA_VID_DST_ADDR 0x07A8
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#define DMA_VID_COMMAND 0x07AC
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#define DMA_VID_STATUS 0x07B0
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#define DMA_VID_ACT_DSCRPTR 0x07B4
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#define CP_ME_CNTL 0x07D0
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#define CP_ME_RAM_ADDR 0x07D4
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#define CP_ME_RAM_RADDR 0x07D8
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#define CP_ME_RAM_DATAH 0x07DC
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#define CP_ME_RAM_DATAL 0x07E0
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#define CP_CSQ_ADDR 0x07F0
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#define CP_CSQ_DATA 0x07F4
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#define CP_CSQ_STAT 0x07F8
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#define DISP_MISC_CNTL 0x0D00
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# define SOFT_RESET_GRPH_PP (1 << 0)
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#define DAC_MACRO_CNTL 0x0D04
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@ -713,6 +786,10 @@
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/* first capture unit */
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#define VID_BUFFER_CONTROL 0x0900
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#define CAP_INT_CNTL 0x0908
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#define CAP_INT_STATUS 0x090C
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#define FCP_CNTL 0x0910
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#define CAP0_BUF0_OFFSET 0x0920
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#define CAP0_BUF1_OFFSET 0x0924
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#define CAP0_BUF0_EVEN_OFFSET 0x0928
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@ -778,7 +855,6 @@
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#define CAP0_VBI3_OFFSET 0x0984
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#define CAP0_ANC2_OFFSET 0x0988
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#define CAP0_ANC3_OFFSET 0x098C
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#define VID_BUFFER_CONTROL 0x0900
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/* second capture unit */
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@ -872,6 +948,8 @@
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#define SRC_PITCH_OFFSET 0x1428
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#define SRC_X 0x1414
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#define SRC_Y 0x1418
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#define DST_WIDTH_X 0x1588
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#define DST_HEIGHT_WIDTH_8 0x158C
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#define SRC_X_Y 0x1590
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#define SRC_Y_X 0x1434
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#define DST_Y_X 0x1438
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@ -1134,6 +1212,23 @@
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/* RAGE THEATER REGISTERS */
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#define DMA_VIPH0_COMMAND 0x0A00
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#define DMA_VIPH1_COMMAND 0x0A04
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#define DMA_VIPH2_COMMAND 0x0A08
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#define DMA_VIPH3_COMMAND 0x0A0C
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#define DMA_VIPH_STATUS 0x0A10
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#define DMA_VIPH_CHUNK_0 0x0A18
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#define DMA_VIPH_CHUNK_1_VAL 0x0A1C
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#define DMA_VIP0_TABLE_ADDR 0x0A20
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#define DMA_VIPH0_ACTIVE 0x0A24
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#define DMA_VIP1_TABLE_ADDR 0x0A30
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#define DMA_VIPH1_ACTIVE 0x0A34
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#define DMA_VIP2_TABLE_ADDR 0x0A40
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#define DMA_VIPH2_ACTIVE 0x0A44
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#define DMA_VIP3_TABLE_ADDR 0x0A50
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#define DMA_VIPH3_ACTIVE 0x0A54
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#define DMA_VIPH_ABORT 0x0A88
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#define VIPH_CH0_DATA 0x0c00
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#define VIPH_CH1_DATA 0x0c04
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#define VIPH_CH2_DATA 0x0c08
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@ -17,7 +17,7 @@
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* Rage128(pro) stuff of this driver.
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*/
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#define RADEON_VID_VERSION "1.1.0"
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#define RADEON_VID_VERSION "1.1.1"
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/*
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It's entirely possible this major conflicts with something else
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@ -221,7 +221,11 @@ static video_registers_t vregs[] =
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DECLARE_VREG(OV0_FOUR_TAP_COEF_3),
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DECLARE_VREG(OV0_FOUR_TAP_COEF_4),
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DECLARE_VREG(OV0_FLAG_CNTL),
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#ifdef RAGE128
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DECLARE_VREG(OV0_COLOUR_CNTL),
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#else
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DECLARE_VREG(OV0_SLICE_CNTL),
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#endif
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DECLARE_VREG(OV0_VID_KEY_CLR),
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DECLARE_VREG(OV0_VID_KEY_MSK),
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DECLARE_VREG(OV0_GRAPHICS_KEY_CLR),
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@ -382,11 +386,11 @@ static void radeon_vid_display_video( void )
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OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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#ifdef RAGE128
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OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) |
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(besr.saturation << 8) |
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(besr.saturation << 16));
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#endif
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if(besr.ckey_on)
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{
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OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
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@ -663,7 +667,9 @@ static void radeon_vid_frame_sel(int frame)
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static void radeon_vid_make_default(void)
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{
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#ifdef RAGE128
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OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */
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#endif
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besr.deinterlace_pattern = 0x900AAAAA;
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OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
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besr.deinterlace_on=1;
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@ -673,10 +679,12 @@ static void radeon_vid_make_default(void)
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static void radeon_vid_preset(void)
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{
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#ifdef RAGE128
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unsigned tmp;
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tmp = INREG(OV0_COLOUR_CNTL);
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besr.saturation = (tmp>>8)&0x1f;
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besr.brightness = tmp & 0x7f;
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#endif
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besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR);
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besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN);
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}
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@ -914,8 +922,10 @@ static void radeon_param_buff_fill( void )
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len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n");
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len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n");
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len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off");
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#ifdef RAGE128
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len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness);
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len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation);
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#endif
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len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off");
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len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern);
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radeon_param_buff_len = len;
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@ -935,6 +945,7 @@ static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_
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static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
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{
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#ifdef RAGE128
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if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0)
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{
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long brightness;
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@ -958,6 +969,7 @@ static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count
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(saturation << 16));
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}
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else
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#endif
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if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0)
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{
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if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1;
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