mirror of https://github.com/mpv-player/mpv
286 lines
8.2 KiB
Plaintext
286 lines
8.2 KiB
Plaintext
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ATI chips hacking
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=================
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Dedicated to ATI's hackers.
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Preface
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~~~~~~~
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This document will compare ATI chips only from point of DAC and video overlay.
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There are lots of difference from 3D point, dual-head support, tv-out support
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and many other things but it's already perfectly different story.
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This document doesn't include information about ATI AIW (All In Wonder) chips.
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What are units on modern ATI chips:
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DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output
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Consists from:
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PLL - (Programable line length) registers
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CRTC - CRT controller
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LCD/DFP scaler
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surface control
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DAC2 - controls CRTC, LCD, DFP monitor's output on second head
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TVDAC - controls Composite Video and Super Video output ports
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Consists from:
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TV_PLL
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TV scaler & sync unit
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TV format convertor (PAL/NTSC)
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TVCAP - controls Video-In port
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MPP - Miscellaneous peripheral port. (includes ImpactTV(2+) - copy
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protection mechanism)
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OV - Video overlay (YUV BES) (include subpictures, gamma correction and
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adaptive deinterlacing)
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CAP0 - Video capturing
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CAP1 - Video capturing (second unit)
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RT - Rage theatre: video encoding and mixing
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MUX - video muxer
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MEM - PCI/AGP bus mastering
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2D - GUI engine
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3D - 3D-OpenGL engine (There are lots of stuff)
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I2C - I2C Bus control
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This document is mainly related only with OV unit ;)
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Video decoding diagram:
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RAM memory: [ App ] Copies YUV image to overlay memory
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| <-- (It's possible to program DMA here)
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overlay memory:[ OV ] performs scaling and YUVtoRGB convertion
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/\
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RGB memory: / \
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/ [ ImpactTV ] performs copy protection filtering
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/ \ (unneeded but presented by default thing;)
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[ CRTC/LCD/DFP DAC ] [ TV DAC ] convert RGB memory to CRTC and NTSC/PAL signals
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[CRTC/LCD/DFP Monitor] [TV-screen]
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History
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~~~~~~~
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What is history of ATI's chips? I can be wrong but below is my vision
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of this question:
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0. I don't know any earlied chips :(
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1. Mach8
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2. Mach16
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3. Mach32
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4. Mach64.
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It's first chip which has support from side of open
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source drivers. Set of mach64 chips is:
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mach64GX (ATI888GX00)
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mach64CX (ATI888CX00)
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mach64CT (ATI264CT)
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mach64ET (ATI264ET)
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mach64VTA3 (ATI264VT)
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mach64VTA4 (ATI264VT)
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mach64VTB (ATI264VTB)
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mach64VT4 (ATI264VT4)
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5. 3D rage chips.
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It seems that these chips have fully compatible by GPU with Mach64
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which is extended by 3D possibilities. Set of 3D rage chips is:
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3D RAGE (GT)
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3D RAGE II+ (GTB)
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3D RAGE IIC (PCI)
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3D RAGE IIC (AGP)
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3D RAGE LT
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3D RAGE LT-G
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3D RAGE PRO (BGA, AGP)
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3D RAGE PRO (BGA, AGP, 1x only)
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3D RAGE PRO (BGA, PCI)
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3D RAGE PRO (PQFP, PCI)
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3D RAGE PRO (PQFP, PCI, limited 3D)
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3D RAGE (XL)
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3D RAGE LT PRO (AGP)
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3D RAGE LT PRO (PCI)
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3D RAGE Mobility (PCI)
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3D RAGE Mobility (AGP)
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6. Rage128 chips.
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These chips have perfectly new GPU which supports memory mapped IO
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space for accelerating port access (It's main cause of incompatibility
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with mach64). Set of Rage128 chips is:
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Rage128 GL RE
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Rage128 GL RF
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Rage128 GL RG
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Rage128 GL RH
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Rage128 GL RI
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Rage128 VR RK
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Rage128 VR RL
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Rage128 VR RM
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Rage128 VR RN
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Rage128 VR RO
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Rage128 Mobility M3 LE
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Rage128 Mobility M3 LF
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7. Rage128Pro chips.
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These chips are successors of Rage128 ones.
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Rage128Pro GL PA
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Rage128Pro GL PB
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Rage128Pro GL PC
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Rage128Pro GL PD
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Rage128Pro GL PE
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Rage128Pro GL PF
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Rage128Pro VR PG
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Rage128Pro VR PH
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Rage128Pro VR PI
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Rage128Pro VR PJ
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Rage128Pro VR PK
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Rage128Pro VR PL
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Rage128Pro VR PM
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Rage128Pro VR PN
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Rage128Pro VR PO
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Rage128Pro VR PP
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Rage128Pro VR PQ
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Rage128Pro VR PR
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Rage128Pro VR TR
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Rage128Pro VR PS
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Rage128Pro VR PT
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Rage128Pro VR PU
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Rage128Pro VR PV
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Rage128Pro VR PW
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Rage128Pro VR PX
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Rage128Pro Ultra U1
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Rage128Pro Ultra U2
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Rage128Pro Ultra U3
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8. Radeon chips.
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Indeed they could be named Rage256 Pro. (With minor changes is fully
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compatible with Rage128 chips).
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Radeon QD
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Radeon QE
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Radeon QF
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Radeon QG
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Radeon VE QY
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Radeon VE QZ
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Radeon M6 LY
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Radeon M6 LZ
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Radeon M7 LW
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9. Radeon2 chips.
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Indeed they could be named Rage512 Pro.
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Radeon2 8500 QL
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Radeon2 7500 QW
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10. Radeon3 and newest are cooming soon, but I hope that they will be fully
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compatible with Radeon1 chips.
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In Radeon famility there were introduced also FX chips: Radeon FX and
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Radeon2 8700 FX. Probably they have the same possibility as other Radeon
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but currently it's unknown for me.
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What about video overlay and DAC?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Currently it's known that there is only difference between
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Mach64 and Rage128 compatible chips:
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- They have different logic of io ports programming!
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- They are incompatible by port numbers!
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But:
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- They use the same program logic from register's name point.
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(Indeed exists slight difference even between Radeon and Rage128
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chips. AFAIK only Radeon has OV0_SLICE_CNTL register which currently
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is not used by driver. But I know only its name ;). Also there
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is difference in slight adjust of BES position but it's configured
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by #ifdef blocks).
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Please compare:
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(The piece of Back-End Scaler programming)
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Sample for Mach64 compatible chips:
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***********************************
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#define SPARSE_IO_BASE 0x03fcu
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#define SPARSE_IO_SELECT 0xfc00u
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#define BLOCK_IO_BASE 0xff00u
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#define BLOCK_IO_SELECT 0x00fcu
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#define MM_IO_SELECT 0x03fcu
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#define BLOCK_SELECT 0x0400u
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#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT)
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#define IO_BYTE_SELECT 0x0003u
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#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT)
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#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT)
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#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \
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(SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \
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SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT))
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#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0)
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#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect)
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...
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#define OVERLAY_Y_X_START BlockIOTag(0x100u)
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#define OVERLAY_Y_X_END BlockIOTag(0x101u)
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...
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#define OUTREG(_Register, _Value) \
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MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
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(_Register) & MM_IO_SELECT, _Value)
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...
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OUTREG(OVERLAY_Y_X_START,((drw_x)<<16)|(drw_y)|(1<<31));
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OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h));
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Sample for Rage128 compatible chips:
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************************************
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#define OV0_Y_X_START 0x0400
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#define OV0_Y_X_END 0x0404
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...
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#define INREG(addr) readl((rage_mmio_base)+addr)
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#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr)
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...
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rage_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RAGE_REGSIZE);
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...
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#ifdef RADEON
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#define X_ADJUST 8
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#else /* rage128 */
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#define X_ADJUST 0
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#endif
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OUTREG(OV0_Y_X_START,(drw_x+X_ADJUST)|(drw_y<<16));
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OUTREG(OV0_Y_X_END,(drw_x+drw_w+X_ADJUST)|(drw_y+drw_h)<<16));
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Thus - these chips have almost the same logic from register's name point.
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(except the fact that they have swapped 16-bit halfs).
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Yes - programming of Rage128 is much simpler of Mach64.
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What about other ATI's chips?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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I suggest you have latest copy of GATOS-CVS:
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http://www.linuxvideo.org
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GATOS was designed and introduced as General ATI TV and Overlay Sowfware.
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You will be able to find out there a lots of useful hacking utilities
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(at location gatos-ati/gatos):
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gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X.
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(it's more useful for Win9x to hack their values).
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xatitv - For working with tv-in (currently is under hard development)
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atitvout- For working with tv-out
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and lot of other stuff.
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BUT: After studing of Gatos and X11 stuffs I've found that they are bad
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optimized for movie playback.
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Please compare:
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radeon_vid - configures video overlay only once and provides DGA to it.
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(doesn't require to be MMX optimized)
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gatos and X11 - configures video overlay at every slice of frame, then
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performs unoptimized copying of source stuff to video memory
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often with using CopyMungedData (it's C-analog of YV12_to_YUY2)
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since there are lacks in yv12 support.
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(is not MMX optimized that's gladly accepted, but probably
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will be never optimized due portability).
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Conslusion:
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~~~~~~~~~~~
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That's all folk!
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