2002-01-04 10:32:26 +00:00
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/*
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(C) 2002 - library implementation by Nick Kyrshev
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XFree86 3.3.3 scanpci.c, modified for GATOS/win/gfxdump by <EFBFBD>yvind Aabling.
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*/
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/* $XConsortium: scanpci.c /main/25 1996/10/27 11:48:40 kaleb $ */
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/*
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* name: scanpci.c
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*
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* purpose: This program will scan for and print details of
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* devices on the PCI bus.
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* author: Robin Cutshaw (robin@xfree86.org)
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*
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* supported O/S's: SVR4, UnixWare, SCO, Solaris,
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* FreeBSD, NetBSD, 386BSD, BSDI BSD/386,
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* Linux, Mach/386, ISC
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* DOS (WATCOM 9.5 compiler)
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*
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* compiling: [g]cc scanpci.c -o scanpci
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* for SVR4 (not Solaris), UnixWare use:
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* [g]cc -DSVR4 scanpci.c -o scanpci
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* for DOS, watcom 9.5:
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* wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c
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* and link with PharLap or other dos extender for exe
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*
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*/
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/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ */
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/*
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* Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the names of the above listed copyright holder(s)
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* not be used in advertising or publicity pertaining to distribution of
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* the software without specific, written prior permission. The above listed
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* copyright holder(s) make(s) no representations about the suitability of this
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* software for any purpose. It is provided "as is" without express or
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* implied warranty.
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*
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* THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
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* TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
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* LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
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* DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
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* IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
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* OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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2002-01-15 08:33:09 +00:00
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#include "libdha.h"
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#include <errno.h>
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#include <string.h>
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2002-01-04 10:32:26 +00:00
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#include <stdio.h>
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2002-01-15 08:33:09 +00:00
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#ifdef __unix__
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#include <unistd.h>
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2002-01-04 10:32:26 +00:00
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#endif
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2002-01-15 08:33:09 +00:00
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#include "AsmMacros.h"
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/* OS depended stuff */
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#if defined (linux)
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#include "sysdep/pci_linux.c"
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#elif defined (__FreeBSD__)
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#include "sysdep/pci_freebsd.c"
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#elif defined (__386BSD__)
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#include "sysdep/pci_386bsd.c"
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#elif defined (__NetBSD__)
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#include "sysdep/pci_netbsd.c"
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#elif defined (__OpenBSD__)
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#include "sysdep/pci_openbsd.c"
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#elif defined (__bsdi__)
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#include "sysdep/pci_bsdi.c"
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#elif defined (Lynx)
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#include "sysdep/pci_lynx.c"
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#elif defined (MACH386)
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#include "sysdep/pci_mach386.c"
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#elif defined (__SVR4)
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#if !defined(SVR4)
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#define SVR4
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2002-01-04 10:32:26 +00:00
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#endif
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2002-01-15 08:33:09 +00:00
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#include "sysdep/pci_svr4.c"
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#elif defined (SCO)
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#include "sysdep/pci_sco.c"
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#elif defined (ISC)
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#include "sysdep/pci_isc.c"
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#elif defined (__EMX__)
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#include "sysdep/pci_os2.c"
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2002-01-15 15:31:30 +00:00
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#elif defined (_WIN32) || defined(__CYGWIN__)
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2002-01-15 08:33:09 +00:00
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#include "sysdep/pci_win32.c"
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2002-01-04 10:32:26 +00:00
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#endif
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2002-01-15 08:33:09 +00:00
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#if 0
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2002-01-04 10:32:26 +00:00
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#if defined(__SUNPRO_C) || defined(sun) || defined(__sun)
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#include <sys/psw.h>
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#else
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#include <sys/seg.h>
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#endif
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#include <sys/v86.h>
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#endif
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#if defined(Lynx) && defined(__powerpc__)
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/* let's mimick the Linux Alpha stuff for LynxOS so we don't have
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* to change too much code
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*/
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#include <smem.h>
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static unsigned char *pciConfBase;
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static __inline__ unsigned long
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static swapl(unsigned long val)
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{
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unsigned char *p = (unsigned char *)&val;
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return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0));
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}
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#define BUS(tag) (((tag)>>16)&0xff)
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#define DFN(tag) (((tag)>>8)&0xff)
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#define PCIBIOS_DEVICE_NOT_FOUND 0x86
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#define PCIBIOS_SUCCESSFUL 0x00
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2002-01-15 15:59:53 +00:00
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int pciconfig_read(
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2002-01-04 10:32:26 +00:00
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unsigned char bus,
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unsigned char dev,
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unsigned char offset,
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int len, /* unused, alway 4 */
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unsigned long *val)
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{
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unsigned long _val;
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unsigned long *ptr;
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dev >>= 3;
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if (bus || dev >= 16) {
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*val = 0xFFFFFFFF;
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return PCIBIOS_DEVICE_NOT_FOUND;
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} else {
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ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
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_val = swapl(*ptr);
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}
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*val = _val;
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return PCIBIOS_SUCCESSFUL;
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}
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2002-01-15 15:59:53 +00:00
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int pciconfig_write(
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2002-01-04 10:32:26 +00:00
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unsigned char bus,
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unsigned char dev,
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unsigned char offset,
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int len, /* unused, alway 4 */
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unsigned long val)
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{
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unsigned long _val;
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unsigned long *ptr;
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dev >>= 3;
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_val = swapl(val);
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if (bus || dev >= 16) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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} else {
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ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
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*ptr = _val;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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#endif
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#if !defined(__powerpc__)
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struct pci_config_reg {
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/* start of official PCI config space header */
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union {
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unsigned long device_vendor;
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struct {
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unsigned short vendor;
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unsigned short device;
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} dv;
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} dv_id;
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#define _device_vendor dv_id.device_vendor
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#define _vendor dv_id.dv.vendor
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#define _device dv_id.dv.device
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union {
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unsigned long status_command;
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struct {
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unsigned short command;
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unsigned short status;
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} sc;
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} stat_cmd;
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#define _status_command stat_cmd.status_command
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#define _command stat_cmd.sc.command
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#define _status stat_cmd.sc.status
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union {
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unsigned long class_revision;
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struct {
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unsigned char rev_id;
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unsigned char prog_if;
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unsigned char sub_class;
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unsigned char base_class;
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} cr;
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} class_rev;
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#define _class_revision class_rev.class_revision
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#define _rev_id class_rev.cr.rev_id
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#define _prog_if class_rev.cr.prog_if
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#define _sub_class class_rev.cr.sub_class
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#define _base_class class_rev.cr.base_class
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union {
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unsigned long bist_header_latency_cache;
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struct {
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unsigned char cache_line_size;
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unsigned char latency_timer;
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unsigned char header_type;
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unsigned char bist;
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} bhlc;
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} bhlc;
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#define _bist_header_latency_cache bhlc.bist_header_latency_cache
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#define _cache_line_size bhlc.bhlc.cache_line_size
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#define _latency_timer bhlc.bhlc.latency_timer
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#define _header_type bhlc.bhlc.header_type
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#define _bist bhlc.bhlc.bist
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union {
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struct {
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unsigned long dv_base0;
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unsigned long dv_base1;
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unsigned long dv_base2;
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unsigned long dv_base3;
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unsigned long dv_base4;
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unsigned long dv_base5;
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} dv;
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struct {
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unsigned long bg_rsrvd[2];
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unsigned char primary_bus_number;
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unsigned char secondary_bus_number;
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unsigned char subordinate_bus_number;
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unsigned char secondary_latency_timer;
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unsigned char io_base;
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unsigned char io_limit;
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unsigned short secondary_status;
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unsigned short mem_base;
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unsigned short mem_limit;
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unsigned short prefetch_mem_base;
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unsigned short prefetch_mem_limit;
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} bg;
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} bc;
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#define _base0 bc.dv.dv_base0
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#define _base1 bc.dv.dv_base1
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#define _base2 bc.dv.dv_base2
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#define _base3 bc.dv.dv_base3
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#define _base4 bc.dv.dv_base4
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#define _base5 bc.dv.dv_base5
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#define _primary_bus_number bc.bg.primary_bus_number
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#define _secondary_bus_number bc.bg.secondary_bus_number
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#define _subordinate_bus_number bc.bg.subordinate_bus_number
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#define _secondary_latency_timer bc.bg.secondary_latency_timer
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#define _io_base bc.bg.io_base
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#define _io_limit bc.bg.io_limit
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#define _secondary_status bc.bg.secondary_status
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#define _mem_base bc.bg.mem_base
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#define _mem_limit bc.bg.mem_limit
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#define _prefetch_mem_base bc.bg.prefetch_mem_base
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#define _prefetch_mem_limit bc.bg.prefetch_mem_limit
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unsigned long rsvd1;
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unsigned long rsvd2;
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unsigned long _baserom;
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unsigned long rsvd3;
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unsigned long rsvd4;
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union {
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unsigned long max_min_ipin_iline;
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struct {
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unsigned char int_line;
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unsigned char int_pin;
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unsigned char min_gnt;
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unsigned char max_lat;
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} mmii;
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} mmii;
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#define _max_min_ipin_iline mmii.max_min_ipin_iline
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#define _int_line mmii.mmii.int_line
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#define _int_pin mmii.mmii.int_pin
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#define _min_gnt mmii.mmii.min_gnt
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#define _max_lat mmii.mmii.max_lat
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/* I don't know how accurate or standard this is (DHD) */
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union {
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unsigned long user_config;
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struct {
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unsigned char user_config_0;
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unsigned char user_config_1;
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unsigned char user_config_2;
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unsigned char user_config_3;
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} uc;
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} uc;
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#define _user_config uc.user_config
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#define _user_config_0 uc.uc.user_config_0
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#define _user_config_1 uc.uc.user_config_1
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#define _user_config_2 uc.uc.user_config_2
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#define _user_config_3 uc.uc.user_config_3
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/* end of official PCI config space header */
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unsigned long _pcibusidx;
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unsigned long _pcinumbus;
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unsigned long _pcibuses[16];
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unsigned short _configtype; /* config type found */
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unsigned short _ioaddr; /* config type 1 - private I/O addr */
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unsigned long _cardnum; /* config type 2 - private card number */
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};
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#else
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/* ppc is big endian, swapping bytes is not quite enough
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* to interpret the PCI config registers...
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*/
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|
|
struct pci_config_reg {
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/* start of official PCI config space header */
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|
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union {
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|
|
|
|
unsigned long device_vendor;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned short device;
|
|
|
|
|
unsigned short vendor;
|
|
|
|
|
} dv;
|
|
|
|
|
} dv_id;
|
|
|
|
|
#define _device_vendor dv_id.device_vendor
|
|
|
|
|
#define _vendor dv_id.dv.vendor
|
|
|
|
|
#define _device dv_id.dv.device
|
|
|
|
|
union {
|
|
|
|
|
unsigned long status_command;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned short status;
|
|
|
|
|
unsigned short command;
|
|
|
|
|
} sc;
|
|
|
|
|
} stat_cmd;
|
|
|
|
|
#define _status_command stat_cmd.status_command
|
|
|
|
|
#define _command stat_cmd.sc.command
|
|
|
|
|
#define _status stat_cmd.sc.status
|
|
|
|
|
union {
|
|
|
|
|
unsigned long class_revision;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned char base_class;
|
|
|
|
|
unsigned char sub_class;
|
|
|
|
|
unsigned char prog_if;
|
|
|
|
|
unsigned char rev_id;
|
|
|
|
|
} cr;
|
|
|
|
|
} class_rev;
|
|
|
|
|
#define _class_revision class_rev.class_revision
|
|
|
|
|
#define _rev_id class_rev.cr.rev_id
|
|
|
|
|
#define _prog_if class_rev.cr.prog_if
|
|
|
|
|
#define _sub_class class_rev.cr.sub_class
|
|
|
|
|
#define _base_class class_rev.cr.base_class
|
|
|
|
|
union {
|
|
|
|
|
unsigned long bist_header_latency_cache;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned char bist;
|
|
|
|
|
unsigned char header_type;
|
|
|
|
|
unsigned char latency_timer;
|
|
|
|
|
unsigned char cache_line_size;
|
|
|
|
|
} bhlc;
|
|
|
|
|
} bhlc;
|
|
|
|
|
#define _bist_header_latency_cache bhlc.bist_header_latency_cache
|
|
|
|
|
#define _cache_line_size bhlc.bhlc.cache_line_size
|
|
|
|
|
#define _latency_timer bhlc.bhlc.latency_timer
|
|
|
|
|
#define _header_type bhlc.bhlc.header_type
|
|
|
|
|
#define _bist bhlc.bhlc.bist
|
|
|
|
|
union {
|
|
|
|
|
struct {
|
|
|
|
|
unsigned long dv_base0;
|
|
|
|
|
unsigned long dv_base1;
|
|
|
|
|
unsigned long dv_base2;
|
|
|
|
|
unsigned long dv_base3;
|
|
|
|
|
unsigned long dv_base4;
|
|
|
|
|
unsigned long dv_base5;
|
|
|
|
|
} dv;
|
|
|
|
|
/* ?? */
|
|
|
|
|
struct {
|
|
|
|
|
unsigned long bg_rsrvd[2];
|
|
|
|
|
|
|
|
|
|
unsigned char secondary_latency_timer;
|
|
|
|
|
unsigned char subordinate_bus_number;
|
|
|
|
|
unsigned char secondary_bus_number;
|
|
|
|
|
unsigned char primary_bus_number;
|
|
|
|
|
|
|
|
|
|
unsigned short secondary_status;
|
|
|
|
|
unsigned char io_limit;
|
|
|
|
|
unsigned char io_base;
|
|
|
|
|
|
|
|
|
|
unsigned short mem_limit;
|
|
|
|
|
unsigned short mem_base;
|
|
|
|
|
|
|
|
|
|
unsigned short prefetch_mem_limit;
|
|
|
|
|
unsigned short prefetch_mem_base;
|
|
|
|
|
} bg;
|
|
|
|
|
} bc;
|
|
|
|
|
#define _base0 bc.dv.dv_base0
|
|
|
|
|
#define _base1 bc.dv.dv_base1
|
|
|
|
|
#define _base2 bc.dv.dv_base2
|
|
|
|
|
#define _base3 bc.dv.dv_base3
|
|
|
|
|
#define _base4 bc.dv.dv_base4
|
|
|
|
|
#define _base5 bc.dv.dv_base5
|
|
|
|
|
#define _primary_bus_number bc.bg.primary_bus_number
|
|
|
|
|
#define _secondary_bus_number bc.bg.secondary_bus_number
|
|
|
|
|
#define _subordinate_bus_number bc.bg.subordinate_bus_number
|
|
|
|
|
#define _secondary_latency_timer bc.bg.secondary_latency_timer
|
|
|
|
|
#define _io_base bc.bg.io_base
|
|
|
|
|
#define _io_limit bc.bg.io_limit
|
|
|
|
|
#define _secondary_status bc.bg.secondary_status
|
|
|
|
|
#define _mem_base bc.bg.mem_base
|
|
|
|
|
#define _mem_limit bc.bg.mem_limit
|
|
|
|
|
#define _prefetch_mem_base bc.bg.prefetch_mem_base
|
|
|
|
|
#define _prefetch_mem_limit bc.bg.prefetch_mem_limit
|
|
|
|
|
unsigned long rsvd1;
|
|
|
|
|
unsigned long rsvd2;
|
|
|
|
|
unsigned long _baserom;
|
|
|
|
|
unsigned long rsvd3;
|
|
|
|
|
unsigned long rsvd4;
|
|
|
|
|
union {
|
|
|
|
|
unsigned long max_min_ipin_iline;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned char max_lat;
|
|
|
|
|
unsigned char min_gnt;
|
|
|
|
|
unsigned char int_pin;
|
|
|
|
|
unsigned char int_line;
|
|
|
|
|
} mmii;
|
|
|
|
|
} mmii;
|
|
|
|
|
#define _max_min_ipin_iline mmii.max_min_ipin_iline
|
|
|
|
|
#define _int_line mmii.mmii.int_line
|
|
|
|
|
#define _int_pin mmii.mmii.int_pin
|
|
|
|
|
#define _min_gnt mmii.mmii.min_gnt
|
|
|
|
|
#define _max_lat mmii.mmii.max_lat
|
|
|
|
|
/* I don't know how accurate or standard this is (DHD) */
|
|
|
|
|
union {
|
|
|
|
|
unsigned long user_config;
|
|
|
|
|
struct {
|
|
|
|
|
unsigned char user_config_3;
|
|
|
|
|
unsigned char user_config_2;
|
|
|
|
|
unsigned char user_config_1;
|
|
|
|
|
unsigned char user_config_0;
|
|
|
|
|
} uc;
|
|
|
|
|
} uc;
|
|
|
|
|
#define _user_config uc.user_config
|
|
|
|
|
#define _user_config_0 uc.uc.user_config_0
|
|
|
|
|
#define _user_config_1 uc.uc.user_config_1
|
|
|
|
|
#define _user_config_2 uc.uc.user_config_2
|
|
|
|
|
#define _user_config_3 uc.uc.user_config_3
|
|
|
|
|
/* end of official PCI config space header */
|
|
|
|
|
unsigned long _pcibusidx;
|
|
|
|
|
unsigned long _pcinumbus;
|
|
|
|
|
unsigned long _pcibuses[16];
|
|
|
|
|
unsigned short _ioaddr; /* config type 1 - private I/O addr */
|
|
|
|
|
unsigned short _configtype; /* config type found */
|
|
|
|
|
unsigned long _cardnum; /* config type 2 - private card number */
|
|
|
|
|
};
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define MAX_DEV_PER_VENDOR_CFG1 64
|
|
|
|
|
#define MAX_PCI_DEVICES_PER_BUS 32
|
|
|
|
|
#define MAX_PCI_DEVICES 64
|
|
|
|
|
#define NF ((void (*)())NULL), { 0.0, 0, 0, NULL }
|
|
|
|
|
#define PCI_MULTIFUNC_DEV 0x80
|
|
|
|
|
#define PCI_ID_REG 0x00
|
|
|
|
|
#define PCI_CMD_STAT_REG 0x04
|
|
|
|
|
#define PCI_CLASS_REG 0x08
|
|
|
|
|
#define PCI_HEADER_MISC 0x0C
|
|
|
|
|
#define PCI_MAP_REG_START 0x10
|
|
|
|
|
#define PCI_MAP_ROM_REG 0x30
|
|
|
|
|
#define PCI_INTERRUPT_REG 0x3C
|
|
|
|
|
#define PCI_REG_USERCONFIG 0x40
|
|
|
|
|
|
|
|
|
|
static int pcibus=-1, pcicard=-1, pcifunc=-1 ;
|
|
|
|
|
/*static struct pci_device *pcidev=NULL ;*/
|
|
|
|
|
|
|
|
|
|
#if defined(__alpha__)
|
|
|
|
|
#define PCI_EN 0x00000000
|
|
|
|
|
#else
|
|
|
|
|
#define PCI_EN 0x80000000
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define PCI_MODE1_ADDRESS_REG 0xCF8
|
|
|
|
|
#define PCI_MODE1_DATA_REG 0xCFC
|
|
|
|
|
|
|
|
|
|
#define PCI_MODE2_ENABLE_REG 0xCF8
|
|
|
|
|
#ifdef PC98
|
|
|
|
|
#define PCI_MODE2_FORWARD_REG 0xCF9
|
|
|
|
|
#else
|
|
|
|
|
#define PCI_MODE2_FORWARD_REG 0xCFA
|
|
|
|
|
#endif
|
2002-01-15 08:33:09 +00:00
|
|
|
|
|
|
|
|
|
/* cpu depended stuff */
|
2002-12-20 21:07:27 +00:00
|
|
|
|
#ifndef CONFIG_SVGAHELPER
|
2002-01-15 08:33:09 +00:00
|
|
|
|
#if defined(__alpha__)
|
|
|
|
|
#include "sysdep/pci_alpha.c"
|
|
|
|
|
#elif defined(__ia64__)
|
|
|
|
|
#include "sysdep/pci_ia64.c"
|
|
|
|
|
#elif defined(__sparc__)
|
|
|
|
|
#include "sysdep/pci_sparc.c"
|
|
|
|
|
#elif defined( __arm32__ )
|
|
|
|
|
#include "sysdep/pci_arm32.c"
|
|
|
|
|
#elif defined(__powerpc__)
|
|
|
|
|
#include "sysdep/pci_powerpc.c"
|
|
|
|
|
#else
|
|
|
|
|
#include "sysdep/pci_x86.c"
|
|
|
|
|
#endif
|
2002-12-20 21:07:27 +00:00
|
|
|
|
#endif
|
2002-01-04 10:32:26 +00:00
|
|
|
|
|
|
|
|
|
static pciinfo_t *pci_lst;
|
|
|
|
|
|
2003-01-04 19:01:36 +00:00
|
|
|
|
static void identify_card(struct pci_config_reg *pcr, int idx)
|
2002-01-04 10:32:26 +00:00
|
|
|
|
{
|
2003-01-04 19:01:36 +00:00
|
|
|
|
/* local overflow test */
|
|
|
|
|
if (idx>=MAX_PCI_DEVICES) return ;
|
|
|
|
|
|
|
|
|
|
pci_lst[idx].bus = pcibus ;
|
|
|
|
|
pci_lst[idx].card = pcicard ;
|
|
|
|
|
pci_lst[idx].func = pcifunc ;
|
2003-03-31 00:14:36 +00:00
|
|
|
|
pci_lst[idx].command = pcr->_status_command & 0xFFFF;
|
2003-01-04 19:01:36 +00:00
|
|
|
|
pci_lst[idx].vendor = pcr->_vendor ;
|
|
|
|
|
pci_lst[idx].device = pcr->_device ;
|
|
|
|
|
pci_lst[idx].base0 = 0xFFFFFFFF ;
|
|
|
|
|
pci_lst[idx].base1 = 0xFFFFFFFF ;
|
|
|
|
|
pci_lst[idx].base2 = 0xFFFFFFFF ;
|
|
|
|
|
pci_lst[idx].baserom = 0x000C0000 ;
|
|
|
|
|
if (pcr->_base0) pci_lst[idx].base0 = pcr->_base0 &
|
2002-01-04 10:32:26 +00:00
|
|
|
|
((pcr->_base0&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
|
2003-01-04 19:01:36 +00:00
|
|
|
|
if (pcr->_base1) pci_lst[idx].base1 = pcr->_base1 &
|
2002-01-04 10:32:26 +00:00
|
|
|
|
((pcr->_base1&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
|
2003-01-04 19:01:36 +00:00
|
|
|
|
if (pcr->_base2) pci_lst[idx].base2 = pcr->_base2 &
|
2002-01-04 10:32:26 +00:00
|
|
|
|
((pcr->_base2&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ;
|
2003-01-04 19:01:36 +00:00
|
|
|
|
if (pcr->_baserom) pci_lst[idx].baserom = pcr->_baserom ;
|
2002-01-04 10:32:26 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*main(int argc, char *argv[])*/
|
|
|
|
|
int pci_scan(pciinfo_t *pci_list,unsigned *num_pci)
|
|
|
|
|
{
|
2003-01-04 19:01:36 +00:00
|
|
|
|
unsigned int idx = 0;
|
2002-01-04 10:32:26 +00:00
|
|
|
|
struct pci_config_reg pcr;
|
|
|
|
|
int do_mode1_scan = 0, do_mode2_scan = 0;
|
|
|
|
|
int func, hostbridges=0;
|
2002-01-15 15:59:53 +00:00
|
|
|
|
int ret = -1;
|
2002-01-04 10:32:26 +00:00
|
|
|
|
|
|
|
|
|
pci_lst = pci_list;
|
2003-01-04 19:01:36 +00:00
|
|
|
|
*num_pci = 0;
|
2002-01-04 10:32:26 +00:00
|
|
|
|
|
2002-01-15 15:59:53 +00:00
|
|
|
|
ret = enable_os_io();
|
|
|
|
|
if (ret != 0)
|
|
|
|
|
return(ret);
|
2002-01-15 08:33:09 +00:00
|
|
|
|
|
|
|
|
|
if((pcr._configtype = pci_config_type()) == 0xFFFF) return ENODEV;
|
2002-01-04 10:32:26 +00:00
|
|
|
|
|
|
|
|
|
/* Try pci config 1 probe first */
|
|
|
|
|
|
|
|
|
|
if ((pcr._configtype == 1) || do_mode1_scan) {
|
|
|
|
|
/*printf("\nPCI probing configuration type 1\n");*/
|
|
|
|
|
|
|
|
|
|
pcr._ioaddr = 0xFFFF;
|
|
|
|
|
|
|
|
|
|
pcr._pcibuses[0] = 0;
|
|
|
|
|
pcr._pcinumbus = 1;
|
|
|
|
|
pcr._pcibusidx = 0;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
/*printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);*/
|
|
|
|
|
|
|
|
|
|
for (pcr._cardnum = 0x0; pcr._cardnum < MAX_PCI_DEVICES_PER_BUS;
|
|
|
|
|
pcr._cardnum += 0x1) {
|
|
|
|
|
func = 0;
|
|
|
|
|
do { /* loop over the different functions, if present */
|
2002-01-15 08:33:09 +00:00
|
|
|
|
pcr._device_vendor = pci_get_vendor(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum,
|
|
|
|
|
func);
|
2002-01-04 10:32:26 +00:00
|
|
|
|
if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
|
|
|
|
|
break; /* nothing there */
|
|
|
|
|
|
|
|
|
|
/*printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n",
|
|
|
|
|
pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func,
|
|
|
|
|
pcr._vendor, pcr._device);*/
|
2002-01-15 08:33:09 +00:00
|
|
|
|
pcibus = pcr._pcibuses[pcr._pcibusidx];
|
|
|
|
|
pcicard = pcr._cardnum;
|
|
|
|
|
pcifunc = func;
|
|
|
|
|
|
|
|
|
|
pcr._status_command = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_CMD_STAT_REG);
|
|
|
|
|
pcr._class_revision = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_CLASS_REG);
|
|
|
|
|
pcr._bist_header_latency_cache = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_HEADER_MISC);
|
|
|
|
|
pcr._base0 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START);
|
|
|
|
|
pcr._base1 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START+4);
|
|
|
|
|
pcr._base2 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START+8);
|
|
|
|
|
pcr._base3 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START+0x0C);
|
|
|
|
|
pcr._base4 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START+0x10);
|
|
|
|
|
pcr._base5 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_REG_START+0x14);
|
|
|
|
|
pcr._baserom = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_MAP_ROM_REG);
|
|
|
|
|
pcr._max_min_ipin_iline = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_INTERRUPT_REG);
|
|
|
|
|
pcr._user_config = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
|
|
|
|
|
pcr._cardnum,func,PCI_REG_USERCONFIG);
|
2002-01-04 10:32:26 +00:00
|
|
|
|
/* check for pci-pci bridges */
|
|
|
|
|
#define PCI_CLASS_MASK 0xff000000
|
|
|
|
|
#define PCI_SUBCLASS_MASK 0x00ff0000
|
|
|
|
|
#define PCI_CLASS_BRIDGE 0x06000000
|
|
|
|
|
#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000
|
|
|
|
|
switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) {
|
|
|
|
|
case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI:
|
|
|
|
|
if (pcr._secondary_bus_number > 0) {
|
|
|
|
|
pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case PCI_CLASS_BRIDGE:
|
|
|
|
|
if ( ++hostbridges > 1) {
|
|
|
|
|
pcr._pcibuses[pcr._pcinumbus] = pcr._pcinumbus;
|
|
|
|
|
pcr._pcinumbus++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) {
|
|
|
|
|
/* not a multi function device */
|
|
|
|
|
func = 8;
|
|
|
|
|
} else {
|
|
|
|
|
func++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (idx++ >= MAX_PCI_DEVICES)
|
|
|
|
|
continue;
|
|
|
|
|
|
2003-01-04 19:01:36 +00:00
|
|
|
|
identify_card(&pcr, (*num_pci)++);
|
2002-01-04 10:32:26 +00:00
|
|
|
|
} while( func < 8 );
|
|
|
|
|
}
|
|
|
|
|
} while (++pcr._pcibusidx < pcr._pcinumbus);
|
|
|
|
|
}
|
2003-01-04 19:01:36 +00:00
|
|
|
|
|
2002-01-04 10:32:26 +00:00
|
|
|
|
#if !defined(__alpha__) && !defined(__powerpc__)
|
|
|
|
|
/* Now try pci config 2 probe (deprecated) */
|
|
|
|
|
|
|
|
|
|
if ((pcr._configtype == 2) || do_mode2_scan) {
|
|
|
|
|
outb(PCI_MODE2_ENABLE_REG, 0xF1);
|
|
|
|
|
outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
|
|
|
|
|
|
|
|
|
|
/*printf("\nPCI probing configuration type 2\n");*/
|
|
|
|
|
|
|
|
|
|
pcr._pcibuses[0] = 0;
|
|
|
|
|
pcr._pcinumbus = 1;
|
|
|
|
|
pcr._pcibusidx = 0;
|
|
|
|
|
idx = 0;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){
|
|
|
|
|
outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
|
|
|
|
|
pcr._device_vendor = inl(pcr._ioaddr);
|
|
|
|
|
outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
|
|
|
|
|
|
|
|
|
|
if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
|
|
|
|
|
continue;
|
|
|
|
|
if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0))
|
|
|
|
|
continue; /* catch ASUS P55TP4XE motherboards */
|
|
|
|
|
|
|
|
|
|
/*printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n",
|
|
|
|
|
pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor,
|
|
|
|
|
pcr._device);*/
|
|
|
|
|
pcibus = pcr._pcibuses[pcr._pcibusidx] ;
|
|
|
|
|
pcicard = pcr._ioaddr ; pcifunc = 0 ;
|
|
|
|
|
|
|
|
|
|
outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
|
|
|
|
|
pcr._status_command = inl(pcr._ioaddr + 0x04);
|
|
|
|
|
pcr._class_revision = inl(pcr._ioaddr + 0x08);
|
|
|
|
|
pcr._bist_header_latency_cache = inl(pcr._ioaddr + 0x0C);
|
|
|
|
|
pcr._base0 = inl(pcr._ioaddr + 0x10);
|
|
|
|
|
pcr._base1 = inl(pcr._ioaddr + 0x14);
|
|
|
|
|
pcr._base2 = inl(pcr._ioaddr + 0x18);
|
|
|
|
|
pcr._base3 = inl(pcr._ioaddr + 0x1C);
|
|
|
|
|
pcr._base4 = inl(pcr._ioaddr + 0x20);
|
|
|
|
|
pcr._base5 = inl(pcr._ioaddr + 0x24);
|
|
|
|
|
pcr._baserom = inl(pcr._ioaddr + 0x30);
|
|
|
|
|
pcr._max_min_ipin_iline = inl(pcr._ioaddr + 0x3C);
|
|
|
|
|
pcr._user_config = inl(pcr._ioaddr + 0x40);
|
|
|
|
|
outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
|
|
|
|
|
|
|
|
|
|
/* check for pci-pci bridges (currently we only know Digital) */
|
|
|
|
|
if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001))
|
|
|
|
|
if (pcr._secondary_bus_number > 0)
|
|
|
|
|
pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
|
|
|
|
|
|
|
|
|
|
if (idx++ >= MAX_PCI_DEVICES)
|
|
|
|
|
continue;
|
|
|
|
|
|
2003-01-04 19:01:36 +00:00
|
|
|
|
identify_card(&pcr, (*num_pci)++);
|
2002-01-04 10:32:26 +00:00
|
|
|
|
}
|
|
|
|
|
} while (++pcr._pcibusidx < pcr._pcinumbus);
|
|
|
|
|
|
|
|
|
|
outb(PCI_MODE2_ENABLE_REG, 0x00);
|
|
|
|
|
}
|
|
|
|
|
|
2003-01-04 19:01:36 +00:00
|
|
|
|
#endif /* !__alpha__ && !__powerpc__ */
|
2002-01-04 10:32:26 +00:00
|
|
|
|
|
|
|
|
|
disable_os_io();
|
|
|
|
|
|
|
|
|
|
return 0 ;
|
|
|
|
|
|
|
|
|
|
}
|
2002-01-15 15:59:53 +00:00
|
|
|
|
|
|
|
|
|
#if !defined(ENOTSUP)
|
|
|
|
|
#if defined(EOPNOTSUPP)
|
|
|
|
|
#define ENOTSUP EOPNOTSUPP
|
|
|
|
|
#else
|
|
|
|
|
#warning "ENOTSUP nor EOPNOTSUPP defined!"
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
2002-01-20 12:12:58 +00:00
|
|
|
|
int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func,
|
|
|
|
|
unsigned char cmd, int len, unsigned long *val)
|
2002-01-15 15:59:53 +00:00
|
|
|
|
{
|
2002-01-20 12:12:58 +00:00
|
|
|
|
int ret;
|
|
|
|
|
|
2002-01-15 15:59:53 +00:00
|
|
|
|
if (len != 4)
|
|
|
|
|
{
|
|
|
|
|
printf("pci_config_read: reading non-dword not supported!\n");
|
|
|
|
|
return(ENOTSUP);
|
|
|
|
|
}
|
|
|
|
|
|
2002-01-20 12:12:58 +00:00
|
|
|
|
ret = enable_os_io();
|
|
|
|
|
if (ret != 0)
|
|
|
|
|
return(ret);
|
|
|
|
|
ret = pci_config_read_long(bus, dev, func, cmd);
|
|
|
|
|
disable_os_io();
|
|
|
|
|
|
|
|
|
|
*val = ret;
|
2002-01-15 15:59:53 +00:00
|
|
|
|
return(0);
|
|
|
|
|
}
|
2002-01-16 08:43:22 +00:00
|
|
|
|
|
|
|
|
|
int enable_app_io( void )
|
|
|
|
|
{
|
|
|
|
|
return enable_os_io();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int disable_app_io( void )
|
|
|
|
|
{
|
|
|
|
|
return disable_os_io();
|
2002-04-19 16:34:04 +00:00
|
|
|
|
}
|