2001-10-19 00:40:19 +00:00
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#include "config.h"
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#include "cpudetect.h"
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2002-05-02 11:00:16 +00:00
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#include "mp_msg.h"
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2001-10-19 00:40:19 +00:00
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2001-11-26 23:08:48 +00:00
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CpuCaps gCpuCaps;
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2001-12-28 18:03:03 +00:00
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#include <stdlib.h>
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2009-01-16 08:43:05 +00:00
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#if ARCH_X86
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2001-10-19 00:40:19 +00:00
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#include <stdio.h>
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2002-11-06 23:54:29 +00:00
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#include <string.h>
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2001-10-19 00:40:19 +00:00
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2004-04-06 17:08:02 +00:00
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#if defined (__NetBSD__) || defined(__OpenBSD__)
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2002-12-07 21:04:54 +00:00
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#include <sys/param.h>
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2002-12-23 01:24:42 +00:00
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#include <sys/sysctl.h>
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#include <machine/cpu.h>
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2009-01-30 23:29:39 +00:00
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
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2001-10-19 00:40:19 +00:00
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#include <sys/types.h>
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#include <sys/sysctl.h>
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2009-01-30 23:29:39 +00:00
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#elif defined(__linux__)
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2001-10-19 00:40:19 +00:00
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#include <signal.h>
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2009-01-30 23:29:39 +00:00
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#elif defined(__MINGW32__) || defined(__CYGWIN__)
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2003-07-19 12:25:18 +00:00
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#include <windows.h>
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2009-01-30 23:29:39 +00:00
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#elif defined(__OS2__)
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2008-02-24 18:09:28 +00:00
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#define INCL_DOS
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#include <os2.h>
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2009-01-30 23:29:39 +00:00
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#elif defined(__AMIGAOS4__)
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2006-02-28 23:24:38 +00:00
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#include <proto/exec.h>
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#endif
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2001-10-19 00:40:19 +00:00
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/* Thanks to the FreeBSD project for some of this cpuid code, and
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* help understanding how to use it. Thanks to the Mesa
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* team for SSE support detection and more cpu detect code.
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*/
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/* I believe this code works. However, it has only been used on a PII and PIII */
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static void check_os_katmai_support( void );
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2001-10-19 02:00:45 +00:00
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// return TRUE if cpuid supported
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2006-02-09 14:08:03 +00:00
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static int has_cpuid(void)
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2001-10-19 00:40:19 +00:00
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{
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2001-10-19 02:00:45 +00:00
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// code from libavcodec:
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2009-01-16 08:43:05 +00:00
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#if ARCH_X86_64
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2009-03-27 18:48:47 +00:00
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return 1;
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2008-11-25 18:36:50 +00:00
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#else
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2009-03-27 18:48:47 +00:00
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long a, c;
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2008-10-16 20:17:56 +00:00
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__asm__ volatile (
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2001-10-19 02:00:45 +00:00
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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2009-03-27 18:48:47 +00:00
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"pushfl\n\t"
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2004-10-21 11:55:20 +00:00
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"pop %0\n\t"
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"mov %0, %1\n\t"
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2001-10-19 02:00:45 +00:00
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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2004-10-21 11:55:20 +00:00
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"xor $0x200000, %0\n\t"
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2001-10-19 02:00:45 +00:00
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"push %0\n\t"
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2009-03-27 18:48:47 +00:00
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"popfl\n\t"
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2001-10-19 02:00:45 +00:00
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/* ... Get the (hopefully modified) EFLAGS */
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2009-03-27 18:48:47 +00:00
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"pushfl\n\t"
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2004-10-21 11:55:20 +00:00
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"pop %0\n\t"
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2001-10-19 02:00:45 +00:00
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: "=a" (a), "=c" (c)
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:
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: "cc"
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);
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2008-05-16 09:42:28 +00:00
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return a != c;
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2009-03-27 18:48:47 +00:00
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#endif
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2001-10-19 00:40:19 +00:00
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}
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static void
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do_cpuid(unsigned int ax, unsigned int *p)
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{
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2001-10-19 02:00:45 +00:00
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#if 0
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2008-10-16 20:17:56 +00:00
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__asm__ volatile(
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2001-10-19 00:40:19 +00:00
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"cpuid;"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax)
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);
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2001-10-19 02:00:45 +00:00
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#else
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// code from libavcodec:
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2008-10-16 20:17:56 +00:00
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__asm__ volatile
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2004-10-21 11:55:20 +00:00
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("mov %%"REG_b", %%"REG_S"\n\t"
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2001-10-19 02:00:45 +00:00
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"cpuid\n\t"
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2004-10-21 11:55:20 +00:00
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"xchg %%"REG_b", %%"REG_S
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2001-12-09 17:03:04 +00:00
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: "=a" (p[0]), "=S" (p[1]),
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2001-10-19 02:00:45 +00:00
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"=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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#endif
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2001-10-19 00:40:19 +00:00
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}
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void GetCpuCaps( CpuCaps *caps)
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{
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unsigned int regs[4];
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unsigned int regs2[4];
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2001-11-26 23:08:48 +00:00
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2001-12-24 10:35:43 +00:00
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memset(caps, 0, sizeof(*caps));
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2003-01-09 18:39:09 +00:00
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caps->isX86=1;
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caps->cl_size=32; /* default */
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2001-10-19 14:02:12 +00:00
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if (!has_cpuid()) {
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2002-05-20 00:55:50 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
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2001-10-19 14:02:12 +00:00
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return;
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}
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do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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2002-05-20 00:55:50 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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2001-12-28 18:03:03 +00:00
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(char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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2001-10-19 14:02:12 +00:00
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if (regs[0]>=0x00000001)
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2001-10-19 13:01:31 +00:00
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{
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2006-05-17 21:10:11 +00:00
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char *tmpstr, *ptmpstr;
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2003-01-09 18:39:09 +00:00
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unsigned cl_size;
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2001-11-26 23:08:48 +00:00
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2001-10-19 00:40:19 +00:00
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do_cpuid(0x00000001, regs2);
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2001-10-20 02:35:31 +00:00
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2001-10-19 14:02:12 +00:00
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caps->cpuType=(regs2[0] >> 8)&0xf;
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2006-05-17 21:10:11 +00:00
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caps->cpuModel=(regs2[0] >> 4)&0xf;
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2005-10-04 21:06:07 +00:00
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// see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
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// System Instructions, Table 3-2: Effective family computation, page 120.
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2001-10-19 14:02:12 +00:00
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if(caps->cpuType==0xf){
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2005-10-04 21:06:07 +00:00
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// use extended family (P4, IA64, K8)
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caps->cpuType=0xf+((regs2[0]>>20)&255);
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2001-10-19 00:40:19 +00:00
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}
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2006-05-17 21:10:11 +00:00
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if(caps->cpuType==0xf || caps->cpuType==6)
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caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
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2001-12-09 17:03:04 +00:00
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caps->cpuStepping=regs2[0] & 0xf;
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2001-10-19 14:02:12 +00:00
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// general feature flags:
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2003-09-19 23:52:41 +00:00
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caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010
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2001-10-19 02:00:45 +00:00
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caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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2009-03-12 10:50:21 +00:00
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caps->hasSSE3 = (regs2[2] & 1); // 0x0000001
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2008-11-30 09:17:21 +00:00
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caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200
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2001-10-19 14:02:12 +00:00
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caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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2003-01-09 18:39:09 +00:00
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cl_size = ((regs2[1] >> 8) & 0xFF)*8;
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if(cl_size) caps->cl_size = cl_size;
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2003-09-19 23:52:41 +00:00
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2006-05-17 21:10:11 +00:00
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ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
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2006-06-25 17:37:58 +00:00
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while(*ptmpstr == ' ') // strip leading spaces
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2006-05-17 21:10:11 +00:00
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ptmpstr++;
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2009-02-09 00:29:26 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
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2003-09-19 23:52:41 +00:00
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free(tmpstr);
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2009-02-09 00:29:26 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
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2006-05-17 21:10:11 +00:00
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caps->cpuType, caps->cpuModel, caps->cpuStepping);
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2003-09-19 23:52:41 +00:00
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2001-10-19 00:40:19 +00:00
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}
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2001-10-19 14:02:12 +00:00
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do_cpuid(0x80000000, regs);
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if (regs[0]>=0x80000001) {
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2002-05-20 00:55:50 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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2001-10-19 14:02:12 +00:00
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do_cpuid(0x80000001, regs2);
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2001-12-28 18:23:35 +00:00
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caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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2001-10-19 14:02:12 +00:00
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caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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2008-11-30 09:17:21 +00:00
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caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040
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2001-10-19 00:40:19 +00:00
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}
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2003-01-09 18:39:09 +00:00
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if(regs[0]>=0x80000006)
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{
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do_cpuid(0x80000006, regs2);
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mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
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caps->cl_size = regs2[2] & 0xFF;
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}
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2005-11-07 16:16:14 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
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2001-10-19 02:00:45 +00:00
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#if 0
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2002-05-02 11:00:16 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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2001-10-19 00:40:19 +00:00
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gCpuCaps.hasMMX,
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gCpuCaps.hasMMX2,
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gCpuCaps.hasSSE,
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gCpuCaps.hasSSE2,
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gCpuCaps.has3DNow,
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gCpuCaps.has3DNowExt );
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2001-10-19 02:00:45 +00:00
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#endif
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2001-10-19 00:40:19 +00:00
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2001-10-19 14:02:12 +00:00
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/* FIXME: Does SSE2 need more OS support, too? */
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2008-02-24 18:04:34 +00:00
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#if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
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|| defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
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2008-02-24 18:09:28 +00:00
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|| defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
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|| defined(__OS2__)
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2001-10-19 14:02:12 +00:00
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if (caps->hasSSE)
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check_os_katmai_support();
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if (!caps->hasSSE)
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caps->hasSSE2 = 0;
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#else
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caps->hasSSE=0;
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caps->hasSSE2 = 0;
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#endif
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2001-11-26 23:08:48 +00:00
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// caps->has3DNow=1;
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// caps->hasMMX2 = 0;
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// caps->hasMMX = 0;
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2001-10-19 14:02:12 +00:00
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2009-04-08 20:21:21 +00:00
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#if !CONFIG_RUNTIME_CPUDETECT
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2009-01-16 08:43:05 +00:00
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#if !HAVE_MMX
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2002-05-20 00:55:50 +00:00
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if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->hasMMX=0;
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#endif
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2009-01-16 08:43:05 +00:00
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#if !HAVE_MMX2
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2002-05-20 00:55:50 +00:00
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if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->hasMMX2=0;
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#endif
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2009-01-16 08:43:05 +00:00
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#if !HAVE_SSE
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2002-05-20 00:55:50 +00:00
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if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->hasSSE=0;
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#endif
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2009-01-16 08:43:05 +00:00
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#if !HAVE_SSE2
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2002-05-20 00:55:50 +00:00
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if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->hasSSE2=0;
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#endif
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2009-01-26 09:29:53 +00:00
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#if !HAVE_AMD3DNOW
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2002-05-20 00:55:50 +00:00
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if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->has3DNow=0;
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#endif
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2009-01-26 09:29:53 +00:00
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#if !HAVE_AMD3DNOWEXT
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2002-05-20 00:55:50 +00:00
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if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
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2002-02-24 01:24:18 +00:00
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caps->has3DNowExt=0;
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#endif
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2009-04-08 20:21:21 +00:00
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#endif // CONFIG_RUNTIME_CPUDETECT
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2001-10-19 00:40:19 +00:00
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}
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2001-10-20 02:35:31 +00:00
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char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
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2006-05-17 21:10:11 +00:00
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char vendor[13];
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2001-10-20 11:16:47 +00:00
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char *retname;
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2004-10-13 09:37:32 +00:00
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int i;
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2001-10-20 02:35:31 +00:00
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2006-07-01 03:56:13 +00:00
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if (NULL==(retname=malloc(256))) {
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2002-05-02 11:00:16 +00:00
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mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
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2001-10-20 11:16:47 +00:00
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exit(1);
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}
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2009-02-23 03:35:07 +00:00
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retname[0] = '\0';
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2001-10-20 11:16:47 +00:00
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2001-12-28 18:03:03 +00:00
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sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
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2001-11-26 23:08:48 +00:00
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|
|
2006-05-17 21:10:11 +00:00
|
|
|
do_cpuid(0x80000000,regs);
|
|
|
|
if (regs[0] >= 0x80000004)
|
|
|
|
{
|
|
|
|
// CPU has built-in namestring
|
|
|
|
for (i = 0x80000002; i <= 0x80000004; i++)
|
|
|
|
{
|
|
|
|
do_cpuid(i, regs);
|
|
|
|
strncat(retname, (char*)regs, 16);
|
|
|
|
}
|
2001-10-20 02:35:31 +00:00
|
|
|
}
|
|
|
|
return retname;
|
|
|
|
}
|
|
|
|
|
2009-01-16 09:44:36 +00:00
|
|
|
#if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
|
2001-10-19 00:40:19 +00:00
|
|
|
static void sigill_handler_sse( int signal, struct sigcontext sc )
|
|
|
|
{
|
2002-05-20 00:55:50 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
|
2001-10-19 00:40:19 +00:00
|
|
|
|
|
|
|
/* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
|
|
|
|
* instructions are 3 bytes long. We must increment the instruction
|
|
|
|
* pointer manually to avoid repeated execution of the offending
|
|
|
|
* instruction.
|
|
|
|
*
|
|
|
|
* If the SIGILL is caused by a divide-by-zero when unmasked
|
|
|
|
* exceptions aren't supported, the SIMD FPU status and control
|
|
|
|
* word will be restored at the end of the test, so we don't need
|
|
|
|
* to worry about doing it here. Besides, we may not be able to...
|
|
|
|
*/
|
|
|
|
sc.eip += 3;
|
|
|
|
|
|
|
|
gCpuCaps.hasSSE=0;
|
|
|
|
}
|
2007-09-14 13:49:28 +00:00
|
|
|
#endif /* __linux__ && _POSIX_SOURCE */
|
2001-10-19 00:40:19 +00:00
|
|
|
|
2009-03-27 18:48:47 +00:00
|
|
|
#if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
|
2003-07-19 12:25:18 +00:00
|
|
|
LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
|
|
|
|
{
|
|
|
|
if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
|
|
|
|
ep->ContextRecord->Eip +=3;
|
|
|
|
gCpuCaps.hasSSE=0;
|
|
|
|
return EXCEPTION_CONTINUE_EXECUTION;
|
|
|
|
}
|
|
|
|
return EXCEPTION_CONTINUE_SEARCH;
|
|
|
|
}
|
2008-10-13 16:23:55 +00:00
|
|
|
#endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
|
2003-07-19 12:25:18 +00:00
|
|
|
|
2008-02-24 18:09:28 +00:00
|
|
|
#ifdef __OS2__
|
|
|
|
ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1,
|
|
|
|
PEXCEPTIONREGISTRATIONRECORD p2,
|
|
|
|
PCONTEXTRECORD p3,
|
|
|
|
PVOID p4 )
|
|
|
|
{
|
|
|
|
if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
|
|
|
|
mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
|
|
|
|
|
|
|
|
p3->ctx_RegEip += 3;
|
|
|
|
gCpuCaps.hasSSE = 0;
|
|
|
|
|
|
|
|
return XCPT_CONTINUE_EXECUTION;
|
|
|
|
}
|
|
|
|
return XCPT_CONTINUE_SEARCH;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2001-10-19 00:40:19 +00:00
|
|
|
/* If we're running on a processor that can do SSE, let's see if we
|
|
|
|
* are allowed to or not. This will catch 2.4.0 or later kernels that
|
|
|
|
* haven't been configured for a Pentium III but are running on one,
|
|
|
|
* and RedHat patched 2.2 kernels that have broken exception handling
|
|
|
|
* support for user space apps that do SSE.
|
|
|
|
*/
|
2006-10-05 00:12:04 +00:00
|
|
|
|
2007-01-10 14:56:23 +00:00
|
|
|
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
|
2006-10-05 00:12:04 +00:00
|
|
|
#define SSE_SYSCTL_NAME "hw.instruction_sse"
|
|
|
|
#elif defined(__APPLE__)
|
|
|
|
#define SSE_SYSCTL_NAME "hw.optional.sse"
|
|
|
|
#endif
|
|
|
|
|
2001-10-19 00:40:19 +00:00
|
|
|
static void check_os_katmai_support( void )
|
|
|
|
{
|
2009-01-16 08:43:05 +00:00
|
|
|
#if ARCH_X86_64
|
2005-01-10 18:33:51 +00:00
|
|
|
gCpuCaps.hasSSE=1;
|
|
|
|
gCpuCaps.hasSSE2=1;
|
2007-01-10 14:56:23 +00:00
|
|
|
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
|
2001-10-19 00:40:19 +00:00
|
|
|
int has_sse=0, ret;
|
|
|
|
size_t len=sizeof(has_sse);
|
|
|
|
|
2006-10-05 00:12:04 +00:00
|
|
|
ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
|
2001-10-19 00:40:19 +00:00
|
|
|
if (ret || !has_sse)
|
|
|
|
gCpuCaps.hasSSE=0;
|
|
|
|
|
2004-04-06 17:08:02 +00:00
|
|
|
#elif defined(__NetBSD__) || defined (__OpenBSD__)
|
|
|
|
#if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
|
2002-12-23 01:24:42 +00:00
|
|
|
int has_sse, has_sse2, ret, mib[2];
|
|
|
|
size_t varlen;
|
|
|
|
|
|
|
|
mib[0] = CTL_MACHDEP;
|
|
|
|
mib[1] = CPU_SSE;
|
|
|
|
varlen = sizeof(has_sse);
|
|
|
|
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
|
|
|
|
ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
|
2008-09-18 15:30:23 +00:00
|
|
|
gCpuCaps.hasSSE = ret >= 0 && has_sse;
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
|
2002-12-23 01:24:42 +00:00
|
|
|
|
|
|
|
mib[1] = CPU_SSE2;
|
|
|
|
varlen = sizeof(has_sse2);
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
|
|
|
|
ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
|
2008-09-18 15:30:23 +00:00
|
|
|
gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
|
2002-12-07 21:04:54 +00:00
|
|
|
#else
|
2002-12-23 01:24:42 +00:00
|
|
|
gCpuCaps.hasSSE = 0;
|
2002-12-07 21:04:54 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
|
|
|
|
#endif
|
2008-10-13 16:23:55 +00:00
|
|
|
#elif defined(__MINGW32__) || defined(__CYGWIN__)
|
2003-07-19 12:25:18 +00:00
|
|
|
LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
|
|
|
|
if ( gCpuCaps.hasSSE ) {
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
|
|
|
|
exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
|
2008-10-16 20:17:56 +00:00
|
|
|
__asm__ volatile ("xorps %xmm0, %xmm0");
|
2003-07-19 12:25:18 +00:00
|
|
|
SetUnhandledExceptionFilter(exc_fil);
|
2008-09-18 15:30:23 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
|
2003-07-19 12:25:18 +00:00
|
|
|
}
|
2008-02-24 18:09:28 +00:00
|
|
|
#elif defined(__OS2__)
|
|
|
|
EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
|
|
|
|
if ( gCpuCaps.hasSSE ) {
|
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
|
|
|
|
DosSetExceptionHandler( &RegRec );
|
2008-10-16 20:17:56 +00:00
|
|
|
__asm__ volatile ("xorps %xmm0, %xmm0");
|
2008-02-24 18:09:28 +00:00
|
|
|
DosUnsetExceptionHandler( &RegRec );
|
2008-09-18 15:30:23 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
|
2008-02-24 18:09:28 +00:00
|
|
|
}
|
2001-10-19 00:40:19 +00:00
|
|
|
#elif defined(__linux__)
|
2007-09-14 13:49:28 +00:00
|
|
|
#if defined(_POSIX_SOURCE)
|
2001-10-19 00:40:19 +00:00
|
|
|
struct sigaction saved_sigill;
|
|
|
|
|
|
|
|
/* Save the original signal handlers.
|
|
|
|
*/
|
|
|
|
sigaction( SIGILL, NULL, &saved_sigill );
|
|
|
|
|
|
|
|
signal( SIGILL, (void (*)(int))sigill_handler_sse );
|
|
|
|
|
|
|
|
/* Emulate test for OSFXSR in CR4. The OS will set this bit if it
|
|
|
|
* supports the extended FPU save and restore required for SSE. If
|
|
|
|
* we execute an SSE instruction on a PIII and get a SIGILL, the OS
|
|
|
|
* doesn't support Streaming SIMD Exceptions, even if the processor
|
|
|
|
* does.
|
|
|
|
*/
|
|
|
|
if ( gCpuCaps.hasSSE ) {
|
2002-05-20 00:55:50 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
|
2001-10-19 00:40:19 +00:00
|
|
|
|
2008-10-16 20:17:56 +00:00
|
|
|
// __asm__ volatile ("xorps %%xmm0, %%xmm0");
|
|
|
|
__asm__ volatile ("xorps %xmm0, %xmm0");
|
2001-10-19 00:40:19 +00:00
|
|
|
|
2008-09-18 15:30:23 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
|
2001-10-19 00:40:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Restore the original signal handlers.
|
|
|
|
*/
|
|
|
|
sigaction( SIGILL, &saved_sigill, NULL );
|
|
|
|
|
|
|
|
/* If we've gotten to here and the XMM CPUID bit is still set, we're
|
|
|
|
* safe to go ahead and hook out the SSE code throughout Mesa.
|
|
|
|
*/
|
2008-09-18 15:30:23 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
|
2001-10-19 00:40:19 +00:00
|
|
|
#else
|
|
|
|
/* We can't use POSIX signal handling to test the availability of
|
|
|
|
* SSE, so we disable it by default.
|
|
|
|
*/
|
2002-05-02 11:00:16 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
|
2001-10-19 00:40:19 +00:00
|
|
|
gCpuCaps.hasSSE=0;
|
2007-09-14 13:49:28 +00:00
|
|
|
#endif /* _POSIX_SOURCE */
|
2001-10-19 00:40:19 +00:00
|
|
|
#else
|
|
|
|
/* Do nothing on other platforms for now.
|
|
|
|
*/
|
2002-05-20 00:55:50 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
|
2001-10-19 00:40:19 +00:00
|
|
|
gCpuCaps.hasSSE=0;
|
|
|
|
#endif /* __linux__ */
|
|
|
|
}
|
2006-11-01 18:41:25 +00:00
|
|
|
#else /* ARCH_X86 */
|
2001-11-26 23:08:48 +00:00
|
|
|
|
2007-12-11 20:27:13 +00:00
|
|
|
#ifdef __APPLE__
|
2003-01-18 19:29:46 +00:00
|
|
|
#include <sys/sysctl.h>
|
2009-01-30 23:29:39 +00:00
|
|
|
#elif defined(__AMIGAOS4__)
|
2007-12-11 22:29:22 +00:00
|
|
|
/* nothing */
|
|
|
|
#else
|
2003-01-18 19:29:46 +00:00
|
|
|
#include <signal.h>
|
|
|
|
#include <setjmp.h>
|
|
|
|
|
|
|
|
static sigjmp_buf jmpbuf;
|
|
|
|
static volatile sig_atomic_t canjump = 0;
|
|
|
|
|
|
|
|
static void sigill_handler (int sig)
|
|
|
|
{
|
|
|
|
if (!canjump) {
|
|
|
|
signal (sig, SIG_DFL);
|
|
|
|
raise (sig);
|
|
|
|
}
|
|
|
|
|
|
|
|
canjump = 0;
|
|
|
|
siglongjmp (jmpbuf, 1);
|
|
|
|
}
|
2007-12-11 20:27:13 +00:00
|
|
|
#endif /* __APPLE__ */
|
2003-01-18 19:29:46 +00:00
|
|
|
|
2001-11-26 23:08:48 +00:00
|
|
|
void GetCpuCaps( CpuCaps *caps)
|
|
|
|
{
|
|
|
|
caps->cpuType=0;
|
2006-05-17 21:10:11 +00:00
|
|
|
caps->cpuModel=0;
|
2001-12-09 17:03:04 +00:00
|
|
|
caps->cpuStepping=0;
|
2001-11-26 23:08:48 +00:00
|
|
|
caps->hasMMX=0;
|
|
|
|
caps->hasMMX2=0;
|
|
|
|
caps->has3DNow=0;
|
|
|
|
caps->has3DNowExt=0;
|
|
|
|
caps->hasSSE=0;
|
|
|
|
caps->hasSSE2=0;
|
2009-03-12 10:50:21 +00:00
|
|
|
caps->hasSSE3=0;
|
2008-11-19 16:41:59 +00:00
|
|
|
caps->hasSSSE3=0;
|
|
|
|
caps->hasSSE4a=0;
|
2001-11-26 23:08:48 +00:00
|
|
|
caps->isX86=0;
|
2003-01-18 19:29:46 +00:00
|
|
|
caps->hasAltiVec = 0;
|
2009-01-16 12:23:52 +00:00
|
|
|
#if HAVE_ALTIVEC
|
2007-12-11 20:27:13 +00:00
|
|
|
#ifdef __APPLE__
|
2003-01-18 19:29:46 +00:00
|
|
|
/*
|
|
|
|
rip-off from ffmpeg altivec detection code.
|
|
|
|
this code also appears on Apple's AltiVec pages.
|
|
|
|
*/
|
|
|
|
{
|
|
|
|
int sels[2] = {CTL_HW, HW_VECTORUNIT};
|
|
|
|
int has_vu = 0;
|
|
|
|
size_t len = sizeof(has_vu);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
|
|
|
|
|
|
|
|
if (err == 0)
|
|
|
|
if (has_vu != 0)
|
|
|
|
caps->hasAltiVec = 1;
|
|
|
|
}
|
2009-01-30 23:29:39 +00:00
|
|
|
#elif defined(__AMIGAOS4__)
|
2006-02-28 23:24:38 +00:00
|
|
|
ULONG result = 0;
|
|
|
|
|
|
|
|
GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
|
|
|
|
if (result == VECTORTYPE_ALTIVEC)
|
|
|
|
caps->hasAltiVec = 1;
|
|
|
|
#else
|
2003-01-18 19:29:46 +00:00
|
|
|
/* no Darwin, do it the brute-force way */
|
|
|
|
/* this is borrowed from the libmpeg2 library */
|
|
|
|
{
|
|
|
|
signal (SIGILL, sigill_handler);
|
|
|
|
if (sigsetjmp (jmpbuf, 1)) {
|
|
|
|
signal (SIGILL, SIG_DFL);
|
|
|
|
} else {
|
|
|
|
canjump = 1;
|
|
|
|
|
2008-10-16 18:59:27 +00:00
|
|
|
__asm__ volatile ("mtspr 256, %0\n\t"
|
2003-01-27 21:47:25 +00:00
|
|
|
"vand %%v0, %%v0, %%v0"
|
2003-01-18 19:29:46 +00:00
|
|
|
:
|
|
|
|
: "r" (-1));
|
|
|
|
|
|
|
|
signal (SIGILL, SIG_DFL);
|
|
|
|
caps->hasAltiVec = 1;
|
|
|
|
}
|
|
|
|
}
|
2007-12-11 20:27:13 +00:00
|
|
|
#endif /* __APPLE__ */
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
|
2003-01-18 19:29:46 +00:00
|
|
|
#endif /* HAVE_ALTIVEC */
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_IA64)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_SPARC)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_ARM)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_PPC)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_ALPHA)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_SGI_MIPS)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_PA_RISC)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_S390)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_S390X)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
|
2004-02-16 23:44:05 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_VAX)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
|
2007-12-11 22:37:36 +00:00
|
|
|
|
2009-01-26 14:36:31 +00:00
|
|
|
if (ARCH_XTENSA)
|
2009-02-09 00:29:26 +00:00
|
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
|
2001-11-26 23:08:48 +00:00
|
|
|
}
|
|
|
|
#endif /* !ARCH_X86 */
|