usbdux: usbduxsigma: changed firmware from ADC polling to IRQ processing
In order to prepare the firmware to work with the EHCI driver the ADC data acquisition is now done by triggering the acquisition with a start of frame interrupt (SOF) and then the collection of the data is done via "data ready" interrupts until all data has been received. Once this has happend then the whole packet is dispatched and at the next SOF the next packet is dispatched. If there are SOF interrupts happening during the data acquisiton it is no longer interupted and only send out the next ISO packet once it has comleted its job. Also now the USBDUXSIGMA has now plenty of time to deal with other interrupts between ADC data readouts so that for example the DIO can now be handled much quicker. Signed-off-by: Bernd Porr <mail@berndporr.me.uk> Signed-off-by: Kyle McMartin <kyle@kernel.org>
This commit is contained in:
Bernd Porr
Kyle McMartin
parent
8be41326ad
commit
dba12691ae
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@ -1,5 +1,5 @@
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; usbdux_firmware.asm
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; Copyright (C) 2010,2011,2015 Bernd Porr, mail@berndporr.me.uk
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; Copyright (C) 2010,2011 Bernd Porr, Bernd.Porr@f2s.com
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; For usbduxsigma.c 0.5+
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;
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; This program is free software; you can redistribute it and/or modify
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@ -20,8 +20,8 @@
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; Firmware: usbduxsigma_firmware.asm for usbduxsigma.c
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; Description: University of Stirling USB DAQ & INCITE Technology Limited
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; Devices: [ITL] USB-DUX-SIGMA (usbduxsigma.ko)
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; Author: Bernd Porr <mail@berndporr.me.uk>
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; Updated: 25 Jun 2015
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; Author: Bernd Porr <Bernd.Porr@f2s.com>
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; Updated: 24 Jul 2011
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; Status: testing
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;
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;;;
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@ -35,14 +35,21 @@
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.equ PWMFLAG,81h ; PWM on or off?
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.equ MAXSMPL,82H ; maximum number of samples, n channellist
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.equ MUXSG0,83H ; content of the MUXSG0 register
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.equ SMPLCTR,84h
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.equ DPTRL,85H
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.equ DPTRH,86h
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.equ ASYNC_ON,87h
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;;; actual code
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.org 0000h ; after reset the processor starts here
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ljmp main ; jump to the main loop
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.org 0003h
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ljmp isr0 ; external interrupt 0: /DRY
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.org 0043h ; the IRQ2-vector
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ljmp jmptbl ; irq service-routine
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.org 0100h ; start of the jump table
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jmptbl: ljmp sudav_isr
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@ -160,6 +167,85 @@ ep4_isr:
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reti
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;;; this is triggered when DRY goes low
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isr0:
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push dps
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push dpl
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push dph
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push dpl1
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push dph1
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push acc
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push psw
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push 00h ; R0
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push 01h ; R1
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push 02h ; R2
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push 03h ; R3
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push 04h ; R4
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push 05h ; R5
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push 06h ; R6
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push 07h ; R7
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mov r0,#ASYNC_ON
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mov a,@r0
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jz noepsubmit
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mov DPS,#0
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mov r0,#DPTRL
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mov dpl,@r0
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inc r0
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mov dph,@r0
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lcall readADCch ; read one channel
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mov r0,#DPTRL
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mov @r0,dpl
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inc r0
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mov @r0,dph
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mov r0,#SMPLCTR
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mov a,@r0
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dec a
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mov @r0,a
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jnz noepsubmit
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mov r0,#ASYNC_ON
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mov @r0,#0
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clr IOA.7 ; START = 0
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;; arm the endpoint and send off the data
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mov DPTR,#EP6BCH ; byte count H
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mov a,#0 ; is zero
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lcall syncdelaywr ; wait until we can write again
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mov r0,#MAXSMPL ; number of samples to transmit
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mov a,@r0 ; get them
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rl a ; a=a*2
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rl a ; a=a*2
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add a,#4 ; four bytes for DIO
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mov DPTR,#EP6BCL ; byte count L
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lcall syncdelaywr ; wait until we can write again
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noepsubmit:
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pop 07h
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pop 06h
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pop 05h
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pop 04h ; R4
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pop 03h ; R3
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pop 02h ; R2
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pop 01h ; R1
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pop 00h ; R0
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pop psw
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pop acc
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pop dph1
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pop dpl1
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pop dph
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pop dpl
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pop dps
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reti
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;;; main program
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;;; basically only initialises the processor and
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@ -211,6 +297,9 @@ initAD:
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mov r0,#MAXSMPL ; length of channellist
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mov @r0,#0 ; we don't want to accumlate samples
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mov r0,#ASYNC_ON ; async enable
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mov @r0,#0 ; we don't want to accumlate samples
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mov OEA,#11100000b ; PortA7,A6,A5 Outputs
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mov IOA,#01100000b ; /CS = 1 and START = 0
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mov dptr,#IFCONFIG ; switch on clock on IFCLK pin
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@ -379,6 +468,10 @@ initeps:
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mov a,#11100000b ; BULK data from here to the host
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movx @DPTR,a ;
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mov dptr,#PORTACFG
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mov a,#1 ; interrupt on pin A0
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lcall syncdelaywr
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;; enable interrupts
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mov dptr,#EPIE ; interrupt enable
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mov a,#10001000b ; enable irq for ep1out,8
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@ -392,8 +485,10 @@ initeps:
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mov a,#2 ; enables SOF (1ms/125us interrupt)
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movx @DPTR,a ;
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setb TCON.0 ; make INT0 edge triggered, falling edge
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mov EIE,#00000001b ; enable INT2/USBINT in the 8051's SFR
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mov IE,#80h ; IE, enable all interrupts
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mov IE,#81h ; IE, enable all interrupts and INT0
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ret
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@ -401,10 +496,6 @@ initeps:
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;;; Reads one ADC channel from the converter and stores
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;;; the result at dptr
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readADCch:
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;; we do polling: we wait until DATA READY is zero
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mov a,IOA ; get /DRDY
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jb ACC.0,readADCch ; wait until data ready (DRDY=0)
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;; reading data is done by just dropping /CS and start reading and
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;; while keeping the IN signal to the ADC inactive
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clr IOA.5 ; /cs to 0
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@ -460,7 +551,8 @@ sof_isr:
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anl a,#20H ; full?
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jnz epfull ; EP6-buffer is full
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clr IOA.7 ; stop converter, START = 0
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mov a,IOA ; conversion running?
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jb ACC.7,epfull
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;; make sure that we are starting with the first channel
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mov r0,#MUXSG0 ;
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@ -471,8 +563,6 @@ sof_isr:
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setb IOA.7 ; start converter, START = 1
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;; get the data from the ADC as fast as possible and transfer it
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;; to the EP buffer
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mov dptr,#0f800h ; EP6 buffer
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mov a,IOD ; get DIO D
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movx @dptr,a ; store it
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@ -486,30 +576,18 @@ sof_isr:
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mov a,#0 ; just zero
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movx @dptr,a ; pad it up
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inc dptr ; algin along a 32 bit word
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mov r0,#DPTRL
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mov @r0,dpl
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inc r0
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mov @r0,dph
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mov r0,#MAXSMPL ; number of samples to transmit
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mov a,@r0 ; get them
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mov r1,a ; counter
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mov r0,#MAXSMPL
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mov a,@r0
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mov r0,#SMPLCTR
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mov @r0,a
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;; main loop, get all the data
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eptrans:
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lcall readADCch ; get one reading
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djnz r1,eptrans ; do until we have all content transf'd
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clr IOA.7 ; stop converter, START = 0
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;; arm the endpoint and send off the data
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mov DPTR,#EP6BCH ; byte count H
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mov a,#0 ; is zero
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lcall syncdelaywr ; wait until we can write again
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mov r0,#MAXSMPL ; number of samples to transmit
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mov a,@r0 ; get them
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rl a ; a=a*2
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rl a ; a=a*2
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add a,#4 ; four bytes for DIO
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mov DPTR,#EP6BCL ; byte count L
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lcall syncdelaywr ; wait until we can write again
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mov r0,#ASYNC_ON
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mov @r0,#1 ; enable data collection
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epfull:
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;; do the D/A conversion
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@ -697,6 +775,9 @@ pwm_off:
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sjmp over_da
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initsgADchannel:
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mov r0,#ASYNC_ON
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mov @r0,#0 ; make sure that no async activity is on
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mov dptr,#0e781h ; FIFO buffer of EP1OUT
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lcall configADC ; configures the ADC esp sel the channel
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@ -719,9 +800,14 @@ startadc:
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inc dptr
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mov r0,#MAXSMPL
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mov @r0,a ; length of the channel list
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mov r0,#SMPLCTR
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mov @r0,a
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lcall configADC ; configures all registers
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mov r0,#ASYNC_ON ; async enable
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mov @r0,#1 ; enable it
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lcall reset_ep6 ; reset FIFO
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;; load new A/D data into EP6
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@ -915,8 +1001,12 @@ ep8_jmp:
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;; read one A/D channel
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ep8_sglchannel:
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mov DPTR,#0fc01h ; EP8 FIFO
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setb IOA.7 ; start converter, START = 1
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;; we do polling: we wait until DATA READY is zero
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sglchwait:
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mov a,IOA ; get /DRDY
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jb ACC.0,sglchwait ; wait until data ready (DRDY=0)
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mov DPTR,#0fc01h ; EP8 FIFO
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lcall readADCch ; get one reading
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clr IOA.7 ; stop the converter, START = 0
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