350 lines
10 KiB
C
350 lines
10 KiB
C
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/*
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* carl9170 firmware - used by the ar9170 wireless device
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*
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* This module contains DMA descriptor related definitions.
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*
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* Copyright (c) 2000-2005 ZyDAS Technology Corporation
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* Copyright (c) 2007-2009 Atheros Communications, Inc.
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* Copyright 2009 Johannes Berg <johannes@sipsolutions.net>
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* Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __CARL9170FW_DMA_H
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#define __CARL9170FW_DMA_H
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#include "config.h"
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#include "types.h"
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#include "compiler.h"
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#include "hw.h"
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#include "ieee80211.h"
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#include "wlan.h"
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struct dma_desc {
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volatile uint16_t status; /* Descriptor status */
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volatile uint16_t ctrl; /* Descriptor control */
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volatile uint16_t dataSize; /* Data size */
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volatile uint16_t totalLen; /* Total length */
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struct dma_desc *lastAddr; /* Last address of this chain */
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union {
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uint8_t *_dataAddr; /* Data buffer address */
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void *dataAddr;
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} __packed;
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struct dma_desc *nextAddr; /* Next TD address */
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} __packed __aligned(4);
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/* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), FW */
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#define AR9170_TERMINATOR_NUMBER_B 10
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#define AR9170_TERMINATOR_NUMBER_INT 1
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#ifdef CONFIG_CARL9170FW_CAB_QUEUE
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#define AR9170_TERMINATOR_NUMBER_CAB CARL9170_INTF_NUM
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#else
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#define AR9170_TERMINATOR_NUMBER_CAB 0
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#endif /* CONFIG_CARL9170FW_CAB_QUEUE */
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#define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
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AR9170_TERMINATOR_NUMBER_INT + \
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AR9170_TERMINATOR_NUMBER_CAB)
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#define AR9170_BLOCK_SIZE (256 + 64)
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#define AR9170_DESCRIPTOR_SIZE (sizeof(struct dma_desc))
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struct ar9170_tx_ba_frame {
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struct ar9170_tx_hwdesc hdr;
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struct ieee80211_ba ba;
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} __packed;
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struct carl9170_tx_ba_superframe {
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struct carl9170_tx_superdesc s;
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struct ar9170_tx_ba_frame f;
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} __packed;
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struct ar9170_tx_null_frame {
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struct ar9170_tx_hwdesc hdr;
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struct ieee80211_hdr null;
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} __packed;
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struct carl9170_tx_null_superframe {
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struct carl9170_tx_superdesc s;
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struct ar9170_tx_null_frame f;
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} __packed;
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#define CARL9170_BA_BUFFER_LEN (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
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#define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
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struct carl9170_sram_reserved {
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union {
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uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
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struct carl9170_tx_ba_superframe ba;
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} ba;
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union {
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uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
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struct carl9170_cmd cmd;
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#ifdef CONFIG_CARL9170FW_WOL
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struct carl9170_tx_null_superframe null;
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#endif /* CONFIG_CARL9170FW_WOL */
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} cmd;
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union {
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uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
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struct carl9170_rsp rsp;
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} rsp;
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union {
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uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
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} bcn;
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};
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/*
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* Memory layout in RAM:
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*
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* 0x100000 +--
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* | terminator descriptors (dma_desc)
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* | - Up (to USB host)
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* | - Down (from USB host)
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* | - TX (5x, to wifi)
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* | - AMPDU TX retry
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* | - RX (from wifi)
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* | - CAB Queue
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* | - FW cmd & req descriptor
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* | - BlockAck descriptor
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* | total: AR9170_TERMINATOR_NUMBER
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* +--
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* | block descriptors (dma_desc)
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* | (AR9170_BLOCK_NUMBER)
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* AR9170_BLOCK_BUFFER_BASE +-- align to multiple of 64
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* | block buffers (AR9170_BLOCK_SIZE each)
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* | (AR9170_BLOCK_NUMBER)
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* approx. 0x117c00 +--
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* | BA buffer (128 bytes)
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* +--
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* | CMD buffer (128 bytes)
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* | - used as NULLFRAME buffer (128 bytes) for WOL
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* +--
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* | RSP buffer (320 bytes)
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* +--
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* | BEACON buffer (256 bytes)
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* +--
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* | unaccounted space / padding
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* +--
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* 0x18000
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*/
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#define CARL9170_SRAM_RESERVED (sizeof(struct carl9170_sram_reserved))
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#define AR9170_FRAME_MEMORY_SIZE (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
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#define BLOCK_ALIGNMENT 64
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#define NONBLOCK_DESCRIPTORS_SIZE \
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(AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
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#define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED \
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(ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
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#define AR9170_BLOCK_NUMBER ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
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(AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
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struct ar9170_data_block {
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uint8_t data[AR9170_BLOCK_SIZE];
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};
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struct ar9170_dma_memory {
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struct dma_desc terminator[AR9170_TERMINATOR_NUMBER];
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struct dma_desc block[AR9170_BLOCK_NUMBER];
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struct ar9170_data_block data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
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struct carl9170_sram_reserved reserved __aligned(BLOCK_ALIGNMENT);
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};
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extern struct ar9170_dma_memory dma_mem;
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#define AR9170_DOWN_BLOCK_RATIO 2
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#define AR9170_RX_BLOCK_RATIO 1
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/* Tx 16*2 = 32 packets => 32*(5*320) */
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#define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
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(AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
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#define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
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/* Error code */
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#define AR9170_ERR_FS_BIT 1
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#define AR9170_ERR_LS_BIT 2
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#define AR9170_ERR_OWN_BITS 3
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#define AR9170_ERR_DATA_SIZE 4
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#define AR9170_ERR_TOTAL_LEN 5
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#define AR9170_ERR_DATA 6
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#define AR9170_ERR_SEQ 7
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#define AR9170_ERR_LEN 8
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/* Status bits definitions */
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/* Own bits definitions */
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#define AR9170_OWN_BITS 0x3
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#define AR9170_OWN_BITS_S 0
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#define AR9170_OWN_BITS_SW 0x0
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#define AR9170_OWN_BITS_HW 0x1
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#define AR9170_OWN_BITS_SE 0x2
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/* Control bits definitions */
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#define AR9170_CTRL_TXFAIL 1
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#define AR9170_CTRL_BAFAIL 2
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#define AR9170_CTRL_FAIL (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
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/* First segament bit */
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#define AR9170_CTRL_LS_BIT 0x100
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/* Last segament bit */
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#define AR9170_CTRL_FS_BIT 0x200
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struct dma_queue {
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struct dma_desc *head;
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struct dma_desc *terminator;
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};
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#define DESC_PAYLOAD(a) ((void *)a->dataAddr)
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#define DESC_PAYLOAD_OFF(a, offset) ((void *)((unsigned long)(a->_dataAddr) + offset))
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struct dma_desc *dma_unlink_head(struct dma_queue *queue);
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void dma_init_descriptors(void);
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void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
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void dma_put(struct dma_queue *q, struct dma_desc *desc);
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static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
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{
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return q->terminator == desc;
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}
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static inline __inline bool queue_empty(struct dma_queue *q)
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{
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return q->head == q->terminator;
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}
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/*
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* Get a completed packet with # descriptors. Return the first
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* descriptor and pointer the head directly by lastAddr->nextAddr
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*/
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static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
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uint16_t bits)
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{
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struct dma_desc *desc = NULL;
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if ((q->head->status & AR9170_OWN_BITS) == bits)
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desc = dma_unlink_head(q);
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return desc;
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}
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static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
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uint16_t bits)
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{
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struct dma_desc *desc = NULL;
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/* AR9170_OWN_BITS_HW will be filtered out here too. */
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if ((q->head->status & AR9170_OWN_BITS) != bits)
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desc = dma_unlink_head(q);
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return desc;
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}
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#define for_each_desc_bits(desc, queue, bits) \
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while ((desc = dma_dequeue_bits(queue, bits)))
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#define for_each_desc_not_bits(desc, queue, bits) \
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while ((desc = dma_dequeue_not_bits(queue, bits)))
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#define for_each_desc(desc, queue) \
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while ((desc = dma_unlink_head(queue)))
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#define __for_each_desc_bits(desc, queue, bits) \
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for (desc = (queue)->head; \
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(desc != (queue)->terminator && \
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(desc->status & AR9170_OWN_BITS) == bits); \
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desc = desc->lastAddr->nextAddr)
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#define __while_desc_bits(desc, queue, bits) \
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for (desc = (queue)->head; \
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(!queue_empty(queue) && \
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(desc->status & AR9170_OWN_BITS) == bits); \
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desc = (queue)->head)
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#define __for_each_desc_continue(desc, queue) \
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for (; desc != (queue)->terminator; \
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desc = (desc)->lastAddr->nextAddr)
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#define __for_each_desc(desc, queue) \
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for (desc = (queue)->head; \
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desc != (queue)->terminator; \
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desc = (desc)->lastAddr->nextAddr)
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#define __for_each_desc_safe(desc, tmp, queue) \
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for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr; \
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desc != (queue)->terminator; \
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desc = tmp, tmp = tmp->lastAddr->nextAddr)
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#define __while_subdesc(desc, queue) \
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for (desc = (queue)->head; \
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desc != (queue)->terminator; \
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desc = (desc)->nextAddr)
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static inline __inline unsigned int queue_len(struct dma_queue *q)
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{
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struct dma_desc *desc;
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unsigned int i = 0;
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__while_subdesc(desc, q)
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i++;
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return i;
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}
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/*
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* rearm a completed packet, so it will be processed agian.
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*/
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static inline __inline void dma_rearm(struct dma_desc *desc)
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{
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/* Set OWN bit to HW */
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desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
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AR9170_OWN_BITS_HW);
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}
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static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
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{
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desc->status = AR9170_OWN_BITS_HW;
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desc->ctrl = 0;
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desc->dataSize = 0;
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desc->totalLen = AR9170_BLOCK_SIZE;
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desc->lastAddr = desc;
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}
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static inline void __check_desc(void)
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{
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struct ar9170_dma_memory mem;
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BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
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BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
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BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
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BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
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BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
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BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
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BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
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BUILD_BUG_ON(sizeof(struct carl9170_tx_null_superframe) > CARL9170_MAX_CMD_LEN);
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}
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#endif /* __CARL9170FW_DMA_H */
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