From cb0451146f2ce4bf8a93890c403262b5308608a4 Mon Sep 17 00:00:00 2001 From: Willy Tarreau Date: Thu, 15 Jul 2021 14:48:21 +0200 Subject: [PATCH] MEDIUM: atomic: simplify the atomic load/store/exchange operations The atomic_load/atomic_store/atomic_xchg operations were all forced to __ATOMIC_SEQ_CST, which results in explicit store or even full barriers even on x86-tso while we do not need them: we're not communicating with external devices for example and are only interested in respecting the proper ordering of loads and stores between each other. These ones being rarely used, the emitted code on x86 remains almost the same (barring a handful of locations). However they will allow to place correct barriers at other places where atomics are accessed a bit lightly. The patch is marked medium because we can never rule out the risk of some bugs on more relaxed platforms due to the rest of the code. --- include/haproxy/atomic.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/haproxy/atomic.h b/include/haproxy/atomic.h index 792c42c0d..70422f4c2 100644 --- a/include/haproxy/atomic.h +++ b/include/haproxy/atomic.h @@ -306,9 +306,9 @@ /* gcc >= 4.7 or clang */ -#define HA_ATOMIC_STORE(val, new) __atomic_store_n(val, new, __ATOMIC_SEQ_CST) -#define HA_ATOMIC_LOAD(val) __atomic_load_n(val, __ATOMIC_SEQ_CST) -#define HA_ATOMIC_XCHG(val, new) __atomic_exchange_n(val, new, __ATOMIC_SEQ_CST) +#define HA_ATOMIC_STORE(val, new) __atomic_store_n(val, new, __ATOMIC_RELEASE) +#define HA_ATOMIC_LOAD(val) __atomic_load_n(val, __ATOMIC_ACQUIRE) +#define HA_ATOMIC_XCHG(val, new) __atomic_exchange_n(val, new, __ATOMIC_ACQ_REL) #define HA_ATOMIC_AND(val, flags) do { __atomic_and_fetch(val, flags, __ATOMIC_SEQ_CST); } while (0) #define HA_ATOMIC_OR(val, flags) do { __atomic_or_fetch(val, flags, __ATOMIC_SEQ_CST); } while (0)