RepoMirrors/haproxy
1
0
Fork 0
mirror of http://git.haproxy.org/git/haproxy.git/ synced 2024-12-26 22:52:13 +00:00
Code Issues Packages Projects Releases Wiki Activity

MINOR: plock: use an ARMv8 instruction barrier for the pause instruction

Browse Source 
As suggested by @AGSaidi in issue #958, on ARMv8 its convenient to use
an "isb" instruction in pl_cpu_relax() to improve fairness. Without it
I've met a few watchdog conditions on valid locks with 16 threads,
indicating that some threads couldn't manage to get it in 2 seconds. I
never happened again with it. In addition, the performance increased
by slightly more than 5% thanks to the reduced contention.

This should be backported as far as 2.2, possibly even 2.0.
This commit is contained in:
Your Name 2020-11-28 15:37:14 +00:00 committed by Willy Tarreau
parent a9ffc41637
commit 1e237d037b
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
include/import/atomic-ops.h
View File

@ -524,10 +524,21 @@
#else #else
/* generic implementations */ /* generic implementations */
#if defined(__aarch64__)
/* This was shown to improve fairness on modern ARMv8 such as Neoverse N1 */
#define pl_cpu_relax() do { \
asm volatile("isb" ::: "memory"); \
} while (0)
#else
#define pl_cpu_relax() do { \ #define pl_cpu_relax() do { \
asm volatile(""); \ asm volatile(""); \
} while (0) } while (0)
#endif
/* full memory barrier */ /* full memory barrier */
#define pl_mb() do { \ #define pl_mb() do { \
__sync_synchronize(); \ __sync_synchronize(); \