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issue-493: Fix for building against ARM targets

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gperftools was failing to build for arm targets for the following reasons:
1. Some ARMv7 instructions used when the target is ARMv6 so those fail to assemble
2. The cache line length is undefined for ARM architectures


git-svn-id: http://gperftools.googlecode.com/svn/trunk@197 6b5cf1ce-ec42-a296-1ba9-69fdba395a50
This commit is contained in:
chappedm@gmail.com 2013-03-11 00:23:03 +00:00
parent bd3b3a7e9a
commit beb78cc05b
2 changed files with 10 additions and 0 deletions
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5
src/base/atomicops-internals-arm-v6plus.h
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@ -95,7 +95,12 @@ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
}
inline void MemoryBarrier() {
#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_6T2__)
uint32_t dest = 0;
__asm__ __volatile__("mcr p15,0,%0,c7,c10,5" :"=&r"(dest) : : "memory");
#else
__asm__ __volatile__("dmb" : : : "memory");
#endif
}
inline Atomic32 Acquire_AtomicExchange(volatile Atomic32* ptr,

5
src/base/basictypes.h
View File

@ -338,6 +338,11 @@ class AssignAttributeStartEnd {
# define CACHELINE_ALIGNED __attribute__((aligned(32)))
# elif (defined(__PPC__) || defined(__PPC64__))
# define CACHELINE_ALIGNED __attribute__((aligned(16)))
# elif (defined(__arm__))
# define CACHELINE_ALIGNED __attribute__((aligned(64)))
// some ARMs have shorter cache lines (ARM1176JZF-S is 32 bytes for example) but obviously 64-byte aligned implies 32-byte aligned
# else
# error Could not determine cache line length - unknown architecture
# endif
#else
# define CACHELINE_ALIGNED