mirror of
https://git.ffmpeg.org/ffmpeg.git
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142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _GNU_SOURCE
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#include "libavutil/cpu.h"
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#include "libavutil/cpu_internal.h"
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#include "libavutil/macros.h"
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#include "libavutil/log.h"
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#include "config.h"
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#if HAVE_GETAUXVAL
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#include <sys/auxv.h>
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#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
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#endif
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#if HAVE_SYS_HWPROBE_H
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#include <sys/hwprobe.h>
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#elif HAVE_ASM_HWPROBE_H
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#include <asm/hwprobe.h>
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#include <sys/syscall.h>
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#include <unistd.h>
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static int __riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
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size_t cpu_count, unsigned long *cpus,
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unsigned int flags)
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{
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return syscall(__NR_riscv_hwprobe, pairs, pair_count, cpu_count, cpus,
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flags);
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}
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#endif
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int ff_get_cpu_flags_riscv(void)
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{
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int ret = 0;
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#if HAVE_SYS_HWPROBE_H || HAVE_ASM_HWPROBE_H
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struct riscv_hwprobe pairs[] = {
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{ RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0 },
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{ RISCV_HWPROBE_KEY_IMA_EXT_0, 0 },
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{ RISCV_HWPROBE_KEY_CPUPERF_0, 0 },
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};
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if (__riscv_hwprobe(pairs, FF_ARRAY_ELEMS(pairs), 0, NULL, 0) == 0) {
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if (pairs[0].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA)
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ret |= AV_CPU_FLAG_RVI;
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if (pairs[1].value & RISCV_HWPROBE_IMA_FD)
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ret |= AV_CPU_FLAG_RVF | AV_CPU_FLAG_RVD;
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#ifdef RISCV_HWPROBE_IMA_V
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if (pairs[1].value & RISCV_HWPROBE_IMA_V)
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ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
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| AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64;
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#endif
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#ifdef RISCV_HWPROBE_EXT_ZBA
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if (pairs[1].value & RISCV_HWPROBE_EXT_ZBA)
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ret |= AV_CPU_FLAG_RVB_ADDR;
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#endif
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#ifdef RISCV_HWPROBE_EXT_ZBB
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if (pairs[1].value & RISCV_HWPROBE_EXT_ZBB)
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ret |= AV_CPU_FLAG_RVB_BASIC;
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#endif
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#ifdef RISCV_HWPROBE_EXT_ZVBB
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if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB)
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ret |= AV_CPU_FLAG_RV_ZVBB;
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#endif
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switch (pairs[2].value & RISCV_HWPROBE_MISALIGNED_MASK) {
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case RISCV_HWPROBE_MISALIGNED_FAST:
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ret |= AV_CPU_FLAG_RV_MISALIGNED;
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break;
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default:
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}
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} else
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#endif
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#if HAVE_GETAUXVAL
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{
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const unsigned long hwcap = getauxval(AT_HWCAP);
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if (hwcap & HWCAP_RV('I'))
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ret |= AV_CPU_FLAG_RVI;
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if (hwcap & HWCAP_RV('F'))
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ret |= AV_CPU_FLAG_RVF;
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if (hwcap & HWCAP_RV('D'))
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ret |= AV_CPU_FLAG_RVD;
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/* The V extension implies all Zve* functional subsets */
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if (hwcap & HWCAP_RV('V'))
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ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
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| AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64;
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}
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#endif
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#ifdef __riscv_i
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ret |= AV_CPU_FLAG_RVI;
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#endif
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#if defined (__riscv_flen) && (__riscv_flen >= 32)
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ret |= AV_CPU_FLAG_RVF;
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#if (__riscv_flen >= 64)
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ret |= AV_CPU_FLAG_RVD;
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#endif
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#endif
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#ifdef __riscv_zba
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ret |= AV_CPU_FLAG_RVB_ADDR;
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#endif
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#ifdef __riscv_zbb
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ret |= AV_CPU_FLAG_RVB_BASIC;
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#endif
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/* If RV-V is enabled statically at compile-time, check the details. */
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#ifdef __riscv_vector
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ret |= AV_CPU_FLAG_RVV_I32;
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#if __riscv_v_elen >= 64
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ret |= AV_CPU_FLAG_RVV_I64;
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#endif
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#if __riscv_v_elen_fp >= 32
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ret |= AV_CPU_FLAG_RVV_F32;
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#if __riscv_v_elen_fp >= 64
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ret |= AV_CPU_FLAG_RVV_F64;
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#endif
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#endif
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#endif
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#ifdef __riscv_zvbb
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ret |= AV_CPU_FLAG_RV_ZVBB;
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#endif
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return ret;
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}
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