ffmpeg/libavutil/riscv
Rémi Denis-Courmont 446b0090cb lavu/float_dsp: avoid reg-stride in R-V V reverse_fmul
This revectors the inner loop to reverse vectors element in vectors,
thus eliminating the negative register stride. Note that RVV does not
have a vector reverse instruction, so this uses a gather.
2023-10-03 20:48:47 +03:00
..
Makefile
asm.S
bswap.h
bswap_rvb.S riscv: factor out the bswap32 assembler 2023-10-02 22:28:21 +03:00
cpu.c lavu: add/use flag for RISC-V Zba extension 2023-07-19 19:29:35 +03:00
cpu.h
fixed_dsp_init.c lavu: add/use flag for RISC-V Zba extension 2023-07-19 19:29:35 +03:00
fixed_dsp_rvv.S
float_dsp_init.c lavu: add/use flag for RISC-V Zba extension 2023-07-19 19:29:35 +03:00
float_dsp_rvv.S lavu/float_dsp: avoid reg-stride in R-V V reverse_fmul 2023-10-03 20:48:47 +03:00
intmath.h
timer.h Revert "lavu/timer: remove gratuitous volatile" 2023-09-28 17:48:18 +03:00