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bbfc0ac9ca
While narrowing clip is nominally a rounding operation, the rounding mode has no arithmetic consequence if the right shift is by zero bits.
102 lines
3.7 KiB
ArmAsm
102 lines
3.7 KiB
ArmAsm
/*
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* Copyright © 2024 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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.option push
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.option norelax
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func ff_h263_h_loop_filter_rvv, zve32x
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lpad 0
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addi a0, a0, -2
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vsetivli zero, 8, e8, mf2, ta, ma
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vlsseg4e8.v v8, (a0), a1
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jal t0, 1f
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vssseg4e8.v v8, (a0), a1
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ret
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1:
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auipc t1, %pcrel_hi(ff_h263_loop_filter_strength)
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vwsubu.vv v14, v10, v9 # p2 - p1
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add t1, t1, a2
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vwsubu.vv v12, v8, v11 # p0 - p3
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vsetvli zero, zero, e16, m1, ta, mu
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vsll.vi v14, v14, 2
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lbu t1, %pcrel_lo(1b)(t1) # strength
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vadd.vv v16, v12, v14
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# Divide by 8 toward 0. v16 is a signed 10-bit value at this point.
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vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0
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slli t2, t1, 1 # 2 * strength
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vadd.vv v16, v16, v18
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# v16 (d) is signed 7-bit, but later arithmetics require 9 bits.
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vsra.vi v16, v16, 3 # d
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vmv.v.x v20, t2
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vmslt.vi v0, v16, 0
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vneg.v v18, v16
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vneg.v v20, v20, v0.t # sign(d) * 2 * strength
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vmax.vv v18, v16, v18 # |d|
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vsub.vv v20, v20, v16 # d1 if strength <= |d| <= 2 * strength
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vmsge.vx v0, v18, t2
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vsrl.vi v14, v12, 16 - 2 # v14 = (v12 < 0) ? 3 : 0
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vmerge.vxm v20, v20, zero, v0 # d1 if strength <= |d|
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vadd.vv v12, v12, v14
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vmsge.vx v0, v18, t1
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vsra.vi v12, v12, 2 # (p0 - p3) / 4
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vmerge.vvm v16, v16, v20, v0 # d1
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vzext.vf2 v24, v8 # p0 as u16 (because vwrsubu.wv does not exist)
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vneg.v v14, v16
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vzext.vf2 v26, v9 # p1 as u16
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vmax.vv v14, v16, v14 # |d1|
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vzext.vf2 v28, v10 # p2 as u16
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vsra.vi v14, v14, 1 # ad1
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vadd.vv v26, v26, v16 # p1 + d1
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vneg.v v18, v14 # -ad1
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vmin.vv v12, v12, v14
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vsub.vv v28, v28, v16 # p2 - d1
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vmax.vv v12, v12, v18 # d2
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vmax.vx v26, v26, zero
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vsub.vv v24, v24, v12 # p0 - d2
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vmax.vx v28, v28, zero
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vsetvli zero, zero, e8, mf2, ta, ma
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vwaddu.wv v30, v12, v11 # p3 + d2
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vncvt.x.x.w v8, v24
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vnclipu.wi v9, v26, 0
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vnclipu.wi v10, v28, 0
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vncvt.x.x.w v11, v30
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jr t0
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endfunc
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.option pop
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func ff_h263_v_loop_filter_rvv, zve32x
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lpad 0
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sub a4, a0, a1
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vsetivli zero, 8, e8, mf2, ta, ma
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vle8.v v10, (a0)
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sub a3, a4, a1
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vle8.v v9, (a4)
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add a5, a0, a1
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vle8.v v8, (a3)
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vle8.v v11, (a5)
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jal t0, 1b
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vse8.v v8, (a3)
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vse8.v v9, (a4)
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vse8.v v10, (a0)
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vse8.v v11, (a5)
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ret
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endfunc
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