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https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
162 lines
4.5 KiB
NASM
162 lines
4.5 KiB
NASM
;******************************************************************************
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;* x86 optimizations for PNG decoding
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;*
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;* Copyright (c) 2008 Loren Merritt <lorenm@u.washington.edu>
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;* Copyright (c) 2012 Ronald S. Bultje <rsbultje@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* 51, Inc., Foundation Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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cextern pw_255
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SECTION .text
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INIT_XMM sse2
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cglobal add_bytes_l2, 4, 6, 2, dst, src1, src2, wa, w, i
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%if ARCH_X86_64
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movsxd waq, wad
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%endif
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xor iq, iq
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; vector loop
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mov wq, waq
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and waq, ~(mmsize*2-1)
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jmp .end_v
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.loop_v:
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movu m0, [src2q+iq]
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movu m1, [src2q+iq+mmsize]
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paddb m0, [src1q+iq]
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paddb m1, [src1q+iq+mmsize]
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movu [dstq+iq ], m0
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movu [dstq+iq+mmsize], m1
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add iq, mmsize*2
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.end_v:
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cmp iq, waq
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jl .loop_v
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; vector loop
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mov waq, wq
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and waq, ~7
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jmp .end_l
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.loop_l:
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movq mm0, [src1q+iq]
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paddb mm0, [src2q+iq]
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movq [dstq+iq ], mm0
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add iq, 8
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.end_l:
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cmp iq, waq
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jl .loop_l
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; scalar loop for leftover
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jmp .end_s
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.loop_s:
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mov wab, [src1q+iq]
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add wab, [src2q+iq]
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mov [dstq+iq], wab
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inc iq
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.end_s:
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cmp iq, wq
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jl .loop_s
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RET
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%macro ADD_PAETH_PRED_FN 1
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cglobal add_png_paeth_prediction, 5, 7, %1, dst, src, top, w, bpp, end, cntr
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%if ARCH_X86_64
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movsxd bppq, bppd
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movsxd wq, wd
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%endif
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lea endq, [dstq+wq-(mmsize/2-1)]
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sub topq, dstq
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sub srcq, dstq
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sub dstq, bppq
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pxor m7, m7
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PUSH dstq
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lea cntrq, [bppq-1]
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shr cntrq, 2 + mmsize/16
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.bpp_loop:
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lea dstq, [dstq+cntrq*(mmsize/2)]
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movh m0, [dstq]
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movh m1, [topq+dstq]
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punpcklbw m0, m7
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punpcklbw m1, m7
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add dstq, bppq
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.loop:
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mova m2, m1
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movh m1, [topq+dstq]
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mova m3, m2
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punpcklbw m1, m7
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mova m4, m2
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psubw m3, m1
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psubw m4, m0
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mova m5, m3
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paddw m5, m4
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%if cpuflag(ssse3)
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pabsw m3, m3
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pabsw m4, m4
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pabsw m5, m5
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%else ; !cpuflag(ssse3)
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psubw m7, m5
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pmaxsw m5, m7
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pxor m6, m6
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pxor m7, m7
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psubw m6, m3
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psubw m7, m4
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pmaxsw m3, m6
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pmaxsw m4, m7
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pxor m7, m7
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%endif ; cpuflag(ssse3)
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mova m6, m4
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pminsw m6, m5
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pcmpgtw m3, m6
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pcmpgtw m4, m5
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mova m6, m4
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pand m4, m3
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pandn m6, m3
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pandn m3, m0
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movh m0, [srcq+dstq]
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pand m6, m1
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pand m2, m4
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punpcklbw m0, m7
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paddw m0, m6
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paddw m3, m2
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paddw m0, m3
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pand m0, [pw_255]
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mova m3, m0
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packuswb m3, m3
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movh [dstq], m3
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add dstq, bppq
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cmp dstq, endq
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jl .loop
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mov dstq, [rsp]
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dec cntrq
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jge .bpp_loop
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POP dstq
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RET
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%endmacro
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INIT_MMX mmxext
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ADD_PAETH_PRED_FN 0
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INIT_MMX ssse3
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ADD_PAETH_PRED_FN 0
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