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db32f75c63
This skips the round-trip to scalar register for the sliding 'x'
coefficients, improving performance by about 5%. The trick here is that
the vector slide-up instruction preserves elements in destination vector
until the slide offset.
The switch from vfslide1up.vf to vslideup.vi also allows the elimination
of data dependencies on consecutive slides. Since the specifications
recommend sticking to power of two offsets, we could slide as follows:
vslideup.vi v8, v0, 2
vslideup.vi v4, v0, 1
vslideup.vi v12, v8, 1
vslideup.vi v16, v8, 2
However in the device under test, this seems to make performance slightly
worse, so this is left for (in)validation with future better hardware.
61 lines
2.0 KiB
ArmAsm
61 lines
2.0 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_opus_postfilter_rvv, zve32f
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flw fa0, 0(a2) // g0
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slli t1, a1, 2
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flw fa1, 4(a2) // g1
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sub t0, a0, t1
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flw fa2, 8(a2) // g2
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addi t1, t0, -2 * 4 // data - (period + 2) = initial &x4
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vsetivli zero, 4, e32, m4, ta, ma
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addi t0, t0, 2 * 4 // data - (period - 2) = initial &x0
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vle32.v v16, (t1)
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addi t3, a1, -2 // maximum parallelism w/o stepping our tail
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1:
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vslidedown.vi v8, v16, 2
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min t1, a3, t3
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vslide1down.vx v12, v16, zero
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vsetvli t1, t1, e32, m4, ta, ma
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vle32.v v0, (t0) // x0
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sub a3, a3, t1
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vslide1down.vx v4, v8, zero
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sh2add t0, t1, t0
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vle32.v v28, (a0)
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addi t2, t1, -4
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vslideup.vi v4, v0, 1
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vslideup.vi v8, v4, 1
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vslideup.vi v12, v8, 1
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vslideup.vi v16, v12, 1
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vfadd.vv v20, v4, v12
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vfadd.vv v24, v0, v16
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vslidedown.vx v16, v0, t2
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vfmacc.vf v28, fa0, v8
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vfmacc.vf v28, fa1, v20
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vfmacc.vf v28, fa2, v24
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vse32.v v28, (a0)
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sh2add a0, t1, a0
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bnez a3, 1b
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ret
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endfunc
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