mirror of https://git.ffmpeg.org/ffmpeg.git
308 lines
10 KiB
ArmAsm
308 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2023 SiFive, Inc. All rights reserved.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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.macro h264_chroma_mc8 type
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func h264_\type\()_chroma_mc8_rvv, zve32x
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csrw vxrm, zero
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slli t2, a5, 3
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mul t1, a5, a4
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sh3add a5, a4, t2
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slli a4, a4, 3
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sub a5, t1, a5
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sub a7, a4, t1
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addi a6, a5, 64
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sub t0, t2, t1
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vsetivli t3, 8, e8, m1, ta, mu
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beqz t1, 2f
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blez a3, 8f
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li t4, 0
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li t2, 0
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li t5, 1
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addi a5, t3, 1
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slli t3, a2, 2
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1: # if (xy != 0)
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add a4, a1, t4
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vsetvli zero, a5, e8, m1, ta, ma
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addi t2, t2, 4
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vle8.v v10, (a4)
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add a4, a4, a2
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vslide1down.vx v11, v10, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v8, v10, a6
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vwmaccu.vx v8, a7, v11
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vsetvli zero, a5, e8, m1, ta, ma
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vle8.v v12, (a4)
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vsetivli zero, 8, e8, m1, ta, ma
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add a4, a4, a2
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vwmaccu.vx v8, t0, v12
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vsetvli zero, a5, e8, m1, ta, ma
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vslide1down.vx v13, v12, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v10, v12, a6
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vwmaccu.vx v8, t1, v13
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vwmaccu.vx v10, a7, v13
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vsetvli zero, a5, e8, m1, ta, ma
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vle8.v v14, (a4)
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vsetivli zero, 8, e8, m1, ta, ma
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add a4, a4, a2
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vwmaccu.vx v10, t0, v14
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vsetvli zero, a5, e8, m1, ta, ma
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vslide1down.vx v15, v14, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v12, v14, a6
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vwmaccu.vx v10, t1, v15
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vwmaccu.vx v12, a7, v15
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vsetvli zero, a5, e8, m1, ta, ma
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vle8.v v14, (a4)
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vsetivli zero, 8, e8, m1, ta, ma
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add a4, a4, a2
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vwmaccu.vx v12, t0, v14
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vsetvli zero, a5, e8, m1, ta, ma
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vslide1down.vx v15, v14, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v16, v14, a6
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vwmaccu.vx v12, t1, v15
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vwmaccu.vx v16, a7, v15
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vsetvli zero, a5, e8, m1, ta, ma
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vle8.v v14, (a4)
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vsetivli zero, 8, e8, m1, ta, ma
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add a4, a0, t4
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add t4, t4, t3
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vwmaccu.vx v16, t0, v14
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vsetvli zero, a5, e8, m1, ta, ma
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vslide1down.vx v14, v14, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vnclipu.wi v15, v8, 6
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vwmaccu.vx v16, t1, v14
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.ifc \type,avg
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vle8.v v9, (a4)
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vaaddu.vv v15, v15, v9
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.endif
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vse8.v v15, (a4)
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add a4, a4, a2
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vnclipu.wi v8, v10, 6
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.ifc \type,avg
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vle8.v v9, (a4)
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vaaddu.vv v8, v8, v9
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.endif
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vse8.v v8, (a4)
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add a4, a4, a2
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vnclipu.wi v8, v12, 6
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.ifc \type,avg
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vle8.v v9, (a4)
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vaaddu.vv v8, v8, v9
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.endif
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vse8.v v8, (a4)
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add a4, a4, a2
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vnclipu.wi v8, v16, 6
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.ifc \type,avg
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vle8.v v9, (a4)
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vaaddu.vv v8, v8, v9
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.endif
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vse8.v v8, (a4)
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blt t2, a3, 1b
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j 8f
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2:
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bnez a4, 4f
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beqz t2, 4f
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blez a3, 8f
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li a4, 0
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li t1, 0
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slli a7, a2, 2
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3: # if ((x8 - xy) == 0 && (y8 -xy) != 0)
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add a5, a1, a4
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vsetvli zero, zero, e8, m1, ta, ma
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addi t1, t1, 4
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vle8.v v8, (a5)
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add a5, a5, a2
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add t2, a5, a2
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vwmulu.vx v10, v8, a6
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vle8.v v8, (a5)
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vwmulu.vx v12, v8, a6
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vle8.v v9, (t2)
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add t2, t2, a2
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add a5, t2, a2
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vwmaccu.vx v10, t0, v8
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vle8.v v8, (t2)
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vle8.v v14, (a5)
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add a5, a0, a4
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add a4, a4, a7
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vwmaccu.vx v12, t0, v9
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vnclipu.wi v15, v10, 6
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vwmulu.vx v10, v9, a6
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.ifc \type,avg
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vle8.v v16, (a5)
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vaaddu.vv v15, v15, v16
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.endif
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vse8.v v15, (a5)
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add a5, a5, a2
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vnclipu.wi v9, v12, 6
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vwmaccu.vx v10, t0, v8
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vwmulu.vx v12, v8, a6
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.ifc \type,avg
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vle8.v v16, (a5)
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vaaddu.vv v9, v9, v16
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.endif
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vse8.v v9, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v10, 6
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vwmaccu.vx v12, t0, v14
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.ifc \type,avg
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vle8.v v16, (a5)
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vaaddu.vv v8, v8, v16
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.endif
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vse8.v v8, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v12, 6
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.ifc \type,avg
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vle8.v v16, (a5)
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vaaddu.vv v8, v8, v16
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.endif
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vse8.v v8, (a5)
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blt t1, a3, 3b
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j 8f
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4:
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beqz a4, 6f
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bnez t2, 6f
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blez a3, 8f
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li a4, 0
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li t2, 0
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addi t0, t3, 1
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slli t1, a2, 2
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5: # if ((x8 - xy) != 0 && (y8 -xy) == 0)
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add a5, a1, a4
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vsetvli zero, t0, e8, m1, ta, ma
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addi t2, t2, 4
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vle8.v v8, (a5)
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add a5, a5, a2
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vslide1down.vx v9, v8, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v10, v8, a6
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vwmaccu.vx v10, a7, v9
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vsetvli zero, t0, e8, m1, ta, ma
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vle8.v v8, (a5)
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add a5, a5, a2
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vslide1down.vx v9, v8, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v12, v8, a6
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vwmaccu.vx v12, a7, v9
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vsetvli zero, t0, e8, m1, ta, ma
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vle8.v v8, (a5)
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add a5, a5, a2
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vslide1down.vx v9, v8, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vwmulu.vx v14, v8, a6
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vwmaccu.vx v14, a7, v9
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vsetvli zero, t0, e8, m1, ta, ma
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vle8.v v8, (a5)
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add a5, a0, a4
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add a4, a4, t1
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vslide1down.vx v9, v8, t5
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vsetivli zero, 8, e8, m1, ta, ma
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vnclipu.wi v16, v10, 6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v16, v16, v18
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.endif
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vse8.v v16, (a5)
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add a5, a5, a2
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vnclipu.wi v10, v12, 6
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vwmulu.vx v12, v8, a6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v10, v10, v18
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.endif
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vse8.v v10, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v14, 6
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vwmaccu.vx v12, a7, v9
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v8, v8, v18
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.endif
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vse8.v v8, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v12, 6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v8, v8, v18
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.endif
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vse8.v v8, (a5)
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blt t2, a3, 5b
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j 8f
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6:
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blez a3, 8f
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li a4, 0
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li t2, 0
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slli a7, a2, 2
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7: # the final else, none of the above conditions are met
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add t0, a1, a4
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vsetvli zero, zero, e8, m1, ta, ma
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add a5, a0, a4
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add a4, a4, a7
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addi t2, t2, 4
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vle8.v v8, (t0)
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add t0, t0, a2
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add t1, t0, a2
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vwmulu.vx v10, v8, a6
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vle8.v v8, (t0)
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add t0, t1, a2
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vle8.v v9, (t1)
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vle8.v v12, (t0)
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vnclipu.wi v13, v10, 6
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vwmulu.vx v10, v8, a6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v13, v13, v18
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.endif
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vse8.v v13, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v10, 6
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vwmulu.vx v10, v9, a6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v8, v8, v18
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.endif
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vse8.v v8, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v10, 6
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vwmulu.vx v10, v12, a6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v8, v8, v18
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.endif
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vse8.v v8, (a5)
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add a5, a5, a2
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vnclipu.wi v8, v10, 6
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.ifc \type,avg
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vle8.v v18, (a5)
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vaaddu.vv v8, v8, v18
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.endif
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vse8.v v8, (a5)
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blt t2, a3, 7b
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8:
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ret
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endfunc
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.endm
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h264_chroma_mc8 put
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h264_chroma_mc8 avg
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