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b2437a45af
x64 always has MMX, MMXEXT, SSE and SSE2 and this means that some functions for MMX, MMXEXT and 3dnow are always overridden by other functions (unless one e.g. explicitly disables SSE2) for x64. So given that the only systems that benefit from these functions are truely ancient 32bit x86s they are removed. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
573 lines
15 KiB
NASM
573 lines
15 KiB
NASM
; XVID MPEG-4 VIDEO CODEC
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;
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; Conversion from gcc syntax to x264asm syntax with modifications
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; by Christophe Gisquet <christophe.gisquet@gmail.com>
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;
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; =========== SSE2 inverse discrete cosine transform ===========
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;
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; Copyright(C) 2003 Pascal Massimino <skal@planet-d.net>
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;
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; Conversion to gcc syntax with modifications
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; by Alexander Strange <astrange@ithinksw.com>
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;
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; Originally from dct/x86_asm/fdct_sse2_skal.asm in Xvid.
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;
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; Vertical pass is an implementation of the scheme:
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; Loeffler C., Ligtenberg A., and Moschytz C.S.:
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; Practical Fast 1D DCT Algorithm with Eleven Multiplications,
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; Proc. ICASSP 1989, 988-991.
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;
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; Horizontal pass is a double 4x4 vector/matrix multiplication,
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; (see also Intel's Application Note 922:
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; http://developer.intel.com/vtune/cbts/strmsimd/922down.htm
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; Copyright (C) 1999 Intel Corporation)
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;
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; More details at http://skal.planet-d.net/coding/dct.html
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;
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; ======= MMX and XMM forward discrete cosine transform =======
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;
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; Copyright(C) 2001 Peter Ross <pross@xvid.org>
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;
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; Originally provided by Intel at AP-922
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; http://developer.intel.com/vtune/cbts/strmsimd/922down.htm
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; (See more app notes at http://developer.intel.com/vtune/cbts/strmsimd/appnotes.htm)
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; but in a limited edition.
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; New macro implements a column part for precise iDCT
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; The routine precision now satisfies IEEE standard 1180-1990.
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;
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; Copyright(C) 2000-2001 Peter Gubanov <peter@elecard.net.ru>
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; Rounding trick Copyright(C) 2000 Michel Lespinasse <walken@zoy.org>
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;
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; http://www.elecard.com/peter/idct.html
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; http://www.linuxvideo.org/mpeg2dec/
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;
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; These examples contain code fragments for first stage iDCT 8x8
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; (for rows) and first stage DCT 8x8 (for columns)
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;
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; conversion to gcc syntax by Michael Niedermayer
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;
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; ======================================================================
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;
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; This file is part of FFmpeg.
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;
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; FFmpeg is free software; you can redistribute it and/or
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; modify it under the terms of the GNU Lesser General Public
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; License as published by the Free Software Foundation; either
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; version 2.1 of the License, or (at your option) any later version.
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;
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; FFmpeg is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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; Lesser General Public License for more details.
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;
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; You should have received a copy of the GNU Lesser General Public License
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; along with FFmpeg; if not, write to the Free Software Foundation,
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; Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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; Similar to tg_1_16 in MMX code
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tan1: times 8 dw 13036
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tan2: times 8 dw 27146
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tan3: times 8 dw 43790
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sqrt2: times 8 dw 23170
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; SSE2 tables
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iTab1: dw 0x4000, 0x539f, 0xc000, 0xac61, 0x4000, 0xdd5d, 0x4000, 0xdd5d
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dw 0x4000, 0x22a3, 0x4000, 0x22a3, 0xc000, 0x539f, 0x4000, 0xac61
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dw 0x3249, 0x11a8, 0x4b42, 0xee58, 0x11a8, 0x4b42, 0x11a8, 0xcdb7
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dw 0x58c5, 0x4b42, 0xa73b, 0xcdb7, 0x3249, 0xa73b, 0x4b42, 0xa73b
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iTab2: dw 0x58c5, 0x73fc, 0xa73b, 0x8c04, 0x58c5, 0xcff5, 0x58c5, 0xcff5
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dw 0x58c5, 0x300b, 0x58c5, 0x300b, 0xa73b, 0x73fc, 0x58c5, 0x8c04
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dw 0x45bf, 0x187e, 0x6862, 0xe782, 0x187e, 0x6862, 0x187e, 0xba41
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dw 0x7b21, 0x6862, 0x84df, 0xba41, 0x45bf, 0x84df, 0x6862, 0x84df
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iTab3: dw 0x539f, 0x6d41, 0xac61, 0x92bf, 0x539f, 0xd2bf, 0x539f, 0xd2bf
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dw 0x539f, 0x2d41, 0x539f, 0x2d41, 0xac61, 0x6d41, 0x539f, 0x92bf
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dw 0x41b3, 0x1712, 0x6254, 0xe8ee, 0x1712, 0x6254, 0x1712, 0xbe4d
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dw 0x73fc, 0x6254, 0x8c04, 0xbe4d, 0x41b3, 0x8c04, 0x6254, 0x8c04
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iTab4: dw 0x4b42, 0x6254, 0xb4be, 0x9dac, 0x4b42, 0xd746, 0x4b42, 0xd746
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dw 0x4b42, 0x28ba, 0x4b42, 0x28ba, 0xb4be, 0x6254, 0x4b42, 0x9dac
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dw 0x3b21, 0x14c3, 0x587e, 0xeb3d, 0x14c3, 0x587e, 0x14c3, 0xc4df
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dw 0x6862, 0x587e, 0x979e, 0xc4df, 0x3b21, 0x979e, 0x587e, 0x979e
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; Similar to rounder_0 in MMX code
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; 4 first similar, then: 4*8->6*16 5*8->4*16 6/7*8->5*16
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walkenIdctRounders: times 4 dd 65536
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times 4 dd 3597
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times 4 dd 2260
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times 4 dd 1203
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times 4 dd 120
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times 4 dd 512
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times 2 dd 0
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pb_127: times 8 db 127
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SECTION .text
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; Temporary storage before the column pass
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%define ROW1 xmm6
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%define ROW3 xmm4
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%define ROW5 xmm5
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%define ROW7 xmm7
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%macro CLEAR_ODD 1
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pxor %1, %1
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%endmacro
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%macro PUT_ODD 1
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pshufhw %1, xmm2, 0x1B
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%endmacro
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%macro MOV32 2
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%if ARCH_X86_32
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movdqa %2, %1
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%endif
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%endmacro
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%macro CLEAR_EVEN 1
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%if ARCH_X86_64
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CLEAR_ODD %1
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%endif
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%endmacro
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%macro PUT_EVEN 1
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%if ARCH_X86_64
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PUT_ODD %1
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%else
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pshufhw xmm2, xmm2, 0x1B
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movdqa %1, xmm2
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%endif
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%endmacro
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%if ARCH_X86_64
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%define ROW0 xmm8
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%define REG0 ROW0
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%define ROW2 xmm9
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%define REG2 ROW2
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%define ROW4 xmm10
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%define REG4 ROW4
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%define ROW6 xmm11
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%define REG6 ROW6
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%define XMMS xmm12
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%define SREG2 REG2
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%define TAN3 xmm13
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%define TAN1 xmm14
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%else
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%define ROW0 [BLOCK + 0*16]
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%define REG0 xmm4
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%define ROW2 [BLOCK + 2*16]
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%define REG2 xmm4
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%define ROW4 [BLOCK + 4*16]
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%define REG4 xmm6
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%define ROW6 [BLOCK + 6*16]
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%define REG6 xmm6
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%define XMMS xmm2
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%define SREG2 xmm7
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%define TAN3 xmm0
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%define TAN1 xmm2
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%endif
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%macro JZ 2
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test %1, %1
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jz .%2
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%endmacro
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%macro JNZ 2
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test %1, %1
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jnz .%2
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%endmacro
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%macro TEST_ONE_ROW 4 ; src, reg, clear, arg
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%3 %4
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movq mm1, [%1]
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por mm1, [%1 + 8]
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paddusb mm1, mm0
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pmovmskb %2, mm1
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%endmacro
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;row1, row2, reg1, reg2, clear1, arg1, clear2, arg2
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%macro TEST_TWO_ROWS 8
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%5 %6
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%7 %8
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movq mm1, [%1 + 0]
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por mm1, [%1 + 8]
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movq mm2, [%2 + 0]
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por mm2, [%2 + 8]
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paddusb mm1, mm0
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paddusb mm2, mm0
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pmovmskb %3, mm1
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pmovmskb %4, mm2
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%endmacro
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; IDCT pass on rows.
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%macro iMTX_MULT 4-5 ; src, table, put, arg, rounder
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movdqa xmm3, [%1]
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movdqa xmm0, xmm3
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pshufd xmm1, xmm3, 0x11 ; 4602
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punpcklqdq xmm0, xmm0 ; 0246
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pmaddwd xmm0, [%2]
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pmaddwd xmm1, [%2+16]
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pshufd xmm2, xmm3, 0xBB ; 5713
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punpckhqdq xmm3, xmm3 ; 1357
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pmaddwd xmm2, [%2+32]
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pmaddwd xmm3, [%2+48]
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paddd xmm0, xmm1
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paddd xmm2, xmm3
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%if %0 == 5
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paddd xmm0, [walkenIdctRounders+%5]
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%endif
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movdqa xmm3, xmm2
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paddd xmm2, xmm0
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psubd xmm0, xmm3
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psrad xmm2, 11
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psrad xmm0, 11
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packssdw xmm2, xmm0
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%3 %4
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%endmacro
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%macro iLLM_HEAD 0
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movdqa TAN3, [tan3]
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movdqa TAN1, [tan1]
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%endmacro
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%macro FIRST_HALF 2 ; %1=dct %2=type(normal,add,put)
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psraw xmm5, 6
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psraw REG0, 6
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psraw TAN3, 6
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psraw xmm3, 6
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; dct coeffs must still be written for AC prediction
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%if %2 == 0
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movdqa [%1+1*16], TAN3
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movdqa [%1+2*16], xmm3
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movdqa [%1+5*16], REG0
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movdqa [%1+6*16], xmm5
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%else
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; Must now load args as gprs are no longer used for masks
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; DEST is set to where address of dest was loaded
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%if ARCH_X86_32
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%if %2 == 2 ; Not enough xmms, store
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movdqa [%1+1*16], TAN3
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movdqa [%1+2*16], xmm3
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movdqa [%1+5*16], REG0
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movdqa [%1+6*16], xmm5
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%endif
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%xdefine DEST r2q ; BLOCK is r0, stride r1
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movifnidn DEST, destm
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movifnidn strideq, stridem
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%else
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%xdefine DEST r0q
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%endif
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lea r3q, [3*strideq]
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%if %2 == 1
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packuswb TAN3, xmm3
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packuswb xmm5, REG0
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movq [DEST + strideq], TAN3
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movhps [DEST + 2*strideq], TAN3
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; REG0 and TAN3 are now available (and likely used in second half)
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%endif
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%endif
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%endmacro
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%macro SECOND_HALF 6 ; %1=dct %2=type(normal,add,put) 3-6: xmms
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psraw %3, 6
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psraw %4, 6
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psraw %5, 6
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psraw %6, 6
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; dct coeffs must still be written for AC prediction
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%if %2 == 0
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movdqa [%1+0*16], %3
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movdqa [%1+3*16], %5
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movdqa [%1+4*16], %6
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movdqa [%1+7*16], %4
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%elif %2 == 1
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packuswb %3, %5
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packuswb %6, %4
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; address of dest may have been loaded
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movq [DEST], %3
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movhps [DEST + r3q], %3
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lea DEST, [DEST + 4*strideq]
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movq [DEST], %6
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movhps [DEST + r3q], %6
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; and now write remainder of first half
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movq [DEST + 2*strideq], xmm5
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movhps [DEST + strideq], xmm5
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%elif %2 == 2
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pxor xmm0, xmm0
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%if ARCH_X86_32
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; free: m3 REG0=m4 m5
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; input: m1, m7, m2, m6
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movq xmm3, [DEST+0*strideq]
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movq xmm4, [DEST+1*strideq]
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punpcklbw xmm3, xmm0
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punpcklbw xmm4, xmm0
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paddsw xmm3, %3
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paddsw xmm4, [%1 + 1*16]
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movq %3, [DEST+2*strideq]
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movq xmm5, [DEST+ r3q]
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punpcklbw %3, xmm0
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punpcklbw xmm5, xmm0
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paddsw %3, [%1 + 2*16]
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paddsw xmm5, %5
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packuswb xmm3, xmm4
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packuswb %3, xmm5
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movq [DEST+0*strideq], xmm3
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movhps [DEST+1*strideq], xmm3
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movq [DEST+2*strideq], %3
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movhps [DEST+ r3q], %3
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lea DEST, [DEST+4*strideq]
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movq xmm3, [DEST+0*strideq]
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movq xmm4, [DEST+1*strideq]
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movq %3, [DEST+2*strideq]
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movq xmm5, [DEST+ r3q]
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punpcklbw xmm3, xmm0
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punpcklbw xmm4, xmm0
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punpcklbw %3, xmm0
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punpcklbw xmm5, xmm0
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paddsw xmm3, %6
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paddsw xmm4, [%1 + 5*16]
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paddsw %3, [%1 + 6*16]
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paddsw xmm5, %4
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packuswb xmm3, xmm4
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packuswb %3, xmm5
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movq [DEST+0*strideq], xmm3
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movhps [DEST+1*strideq], xmm3
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movq [DEST+2*strideq], %3
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movhps [DEST+ r3q], %3
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%else
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; l1:TAN3=m13 l2:m3 l5:REG0=m8 l6=m5
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; input: m1, m7/SREG2=m9, TAN1=m14, REG4=m10
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movq xmm2, [DEST+0*strideq]
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movq xmm4, [DEST+1*strideq]
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movq xmm12, [DEST+2*strideq]
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movq xmm11, [DEST+ r3q]
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punpcklbw xmm2, xmm0
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punpcklbw xmm4, xmm0
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punpcklbw xmm12, xmm0
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punpcklbw xmm11, xmm0
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paddsw xmm2, %3
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paddsw xmm4, TAN3
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paddsw xmm12, xmm3
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paddsw xmm11, %5
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packuswb xmm2, xmm4
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packuswb xmm12, xmm11
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movq [DEST+0*strideq], xmm2
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movhps [DEST+1*strideq], xmm2
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movq [DEST+2*strideq], xmm12
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movhps [DEST+ r3q], xmm12
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lea DEST, [DEST+4*strideq]
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movq xmm2, [DEST+0*strideq]
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movq xmm4, [DEST+1*strideq]
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movq xmm12, [DEST+2*strideq]
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movq xmm11, [DEST+ r3q]
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punpcklbw xmm2, xmm0
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punpcklbw xmm4, xmm0
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punpcklbw xmm12, xmm0
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punpcklbw xmm11, xmm0
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paddsw xmm2, %6
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paddsw xmm4, REG0
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paddsw xmm12, xmm5
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paddsw xmm11, %4
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packuswb xmm2, xmm4
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packuswb xmm12, xmm11
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movq [DEST+0*strideq], xmm2
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movhps [DEST+1*strideq], xmm2
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movq [DEST+2*strideq], xmm12
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movhps [DEST+ r3q], xmm12
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%endif
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%endif
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%endmacro
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; IDCT pass on columns.
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%macro iLLM_PASS 2 ; %1=dct %2=type(normal,add,put)
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movdqa xmm1, TAN3
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movdqa xmm3, TAN1
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pmulhw TAN3, xmm4
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pmulhw xmm1, xmm5
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paddsw TAN3, xmm4
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paddsw xmm1, xmm5
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psubsw TAN3, xmm5
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paddsw xmm1, xmm4
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pmulhw xmm3, xmm7
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pmulhw TAN1, xmm6
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paddsw xmm3, xmm6
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psubsw TAN1, xmm7
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movdqa xmm7, xmm3
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movdqa xmm6, TAN1
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psubsw xmm3, xmm1
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psubsw TAN1, TAN3
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paddsw xmm1, xmm7
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paddsw TAN3, xmm6
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movdqa xmm6, xmm3
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psubsw xmm3, TAN3
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paddsw TAN3, xmm6
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movdqa xmm4, [sqrt2]
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pmulhw xmm3, xmm4
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pmulhw TAN3, xmm4
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paddsw TAN3, TAN3
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paddsw xmm3, xmm3
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movdqa xmm7, [tan2]
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MOV32 ROW2, REG2
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MOV32 ROW6, REG6
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movdqa xmm5, xmm7
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pmulhw xmm7, REG6
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pmulhw xmm5, REG2
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paddsw xmm7, REG2
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psubsw xmm5, REG6
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MOV32 ROW0, REG0
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MOV32 ROW4, REG4
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MOV32 TAN1, [BLOCK]
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movdqa XMMS, REG0
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psubsw REG0, REG4
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paddsw REG4, XMMS
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movdqa XMMS, REG4
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psubsw REG4, xmm7
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paddsw xmm7, XMMS
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movdqa XMMS, REG0
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psubsw REG0, xmm5
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paddsw xmm5, XMMS
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|
movdqa XMMS, xmm5
|
|
psubsw xmm5, TAN3
|
|
paddsw TAN3, XMMS
|
|
movdqa XMMS, REG0
|
|
psubsw REG0, xmm3
|
|
paddsw xmm3, XMMS
|
|
MOV32 [BLOCK], TAN1
|
|
|
|
FIRST_HALF %1, %2
|
|
|
|
movdqa xmm0, xmm7
|
|
movdqa xmm4, REG4
|
|
psubsw xmm7, xmm1
|
|
psubsw REG4, TAN1
|
|
paddsw xmm1, xmm0
|
|
paddsw TAN1, xmm4
|
|
|
|
SECOND_HALF %1, %2, xmm1, xmm7, TAN1, REG4
|
|
%endmacro
|
|
|
|
; IDCT pass on columns, assuming rows 4-7 are zero
|
|
%macro iLLM_PASS_SPARSE 2 ; %1=dct %2=type(normal,put,add)
|
|
pmulhw TAN3, xmm4
|
|
paddsw TAN3, xmm4
|
|
movdqa xmm3, xmm6
|
|
pmulhw TAN1, xmm6
|
|
movdqa xmm1, xmm4
|
|
psubsw xmm3, xmm1
|
|
paddsw xmm1, xmm6
|
|
movdqa xmm6, TAN1
|
|
psubsw TAN1, TAN3
|
|
paddsw TAN3, xmm6
|
|
movdqa xmm6, xmm3
|
|
psubsw xmm3, TAN3
|
|
paddsw TAN3, xmm6
|
|
movdqa xmm4, [sqrt2]
|
|
pmulhw xmm3, xmm4
|
|
pmulhw TAN3, xmm4
|
|
paddsw TAN3, TAN3
|
|
paddsw xmm3, xmm3
|
|
movdqa xmm5, [tan2]
|
|
MOV32 ROW2, SREG2
|
|
pmulhw xmm5, SREG2
|
|
MOV32 ROW0, REG0
|
|
movdqa xmm6, REG0
|
|
psubsw xmm6, SREG2
|
|
paddsw SREG2, REG0
|
|
MOV32 TAN1, [BLOCK]
|
|
movdqa XMMS, REG0
|
|
psubsw REG0, xmm5
|
|
paddsw xmm5, XMMS
|
|
movdqa XMMS, xmm5
|
|
psubsw xmm5, TAN3
|
|
paddsw TAN3, XMMS
|
|
movdqa XMMS, REG0
|
|
psubsw REG0, xmm3
|
|
paddsw xmm3, XMMS
|
|
MOV32 [BLOCK], TAN1
|
|
|
|
FIRST_HALF %1, %2
|
|
|
|
movdqa xmm0, SREG2
|
|
movdqa xmm4, xmm6
|
|
psubsw SREG2, xmm1
|
|
psubsw xmm6, TAN1
|
|
paddsw xmm1, xmm0
|
|
paddsw TAN1, xmm4
|
|
|
|
SECOND_HALF %1, %2, xmm1, SREG2, TAN1, xmm6
|
|
%endmacro
|
|
|
|
%macro IDCT_SSE2 1 ; 0=normal 1=put 2=add
|
|
%if %1 == 0 || ARCH_X86_32
|
|
%define GPR0 r1d
|
|
%define GPR1 r2d
|
|
%define GPR2 r3d
|
|
%define GPR3 r4d
|
|
%define NUM_GPRS 5
|
|
%else
|
|
%define GPR0 r3d
|
|
%define GPR1 r4d
|
|
%define GPR2 r5d
|
|
%define GPR3 r6d
|
|
%define NUM_GPRS 7
|
|
%endif
|
|
%if %1 == 0
|
|
cglobal xvid_idct, 1, NUM_GPRS, 8+7*ARCH_X86_64, block
|
|
%xdefine BLOCK blockq
|
|
%else
|
|
%if %1 == 1
|
|
cglobal xvid_idct_put, 0, NUM_GPRS, 8+7*ARCH_X86_64, dest, stride, block
|
|
%else
|
|
cglobal xvid_idct_add, 0, NUM_GPRS, 8+7*ARCH_X86_64, dest, stride, block
|
|
%endif
|
|
%if ARCH_X86_64
|
|
%xdefine BLOCK blockq
|
|
%else
|
|
mov r0q, blockm
|
|
%xdefine BLOCK r0q
|
|
%endif
|
|
%endif
|
|
movq mm0, [pb_127]
|
|
iMTX_MULT BLOCK + 0*16, iTab1, PUT_EVEN, ROW0, 0*16
|
|
iMTX_MULT BLOCK + 1*16, iTab2, PUT_ODD, ROW1, 1*16
|
|
iMTX_MULT BLOCK + 2*16, iTab3, PUT_EVEN, ROW2, 2*16
|
|
|
|
TEST_TWO_ROWS BLOCK + 3*16, BLOCK + 4*16, GPR0, GPR1, CLEAR_ODD, ROW3, CLEAR_EVEN, ROW4 ; a, c
|
|
JZ GPR0, col1
|
|
iMTX_MULT BLOCK + 3*16, iTab4, PUT_ODD, ROW3, 3*16
|
|
.col1:
|
|
TEST_TWO_ROWS BLOCK + 5*16, BLOCK + 6*16, GPR0, GPR2, CLEAR_ODD, ROW5, CLEAR_EVEN, ROW6 ; a, d
|
|
TEST_ONE_ROW BLOCK + 7*16, GPR3, CLEAR_ODD, ROW7 ; esi
|
|
|
|
iLLM_HEAD
|
|
JNZ GPR1, 2
|
|
JNZ GPR0, 3
|
|
JNZ GPR2, 4
|
|
JNZ GPR3, 5
|
|
iLLM_PASS_SPARSE BLOCK, %1
|
|
jmp .6
|
|
.2:
|
|
iMTX_MULT BLOCK + 4*16, iTab1, PUT_EVEN, ROW4
|
|
.3:
|
|
iMTX_MULT BLOCK + 5*16, iTab4, PUT_ODD, ROW5, 4*16
|
|
JZ GPR2, col2
|
|
.4:
|
|
iMTX_MULT BLOCK + 6*16, iTab3, PUT_EVEN, ROW6, 5*16
|
|
.col2:
|
|
JZ GPR3, col3
|
|
.5:
|
|
iMTX_MULT BLOCK + 7*16, iTab2, PUT_ODD, ROW7, 5*16
|
|
.col3:
|
|
%if ARCH_X86_32
|
|
iLLM_HEAD
|
|
%endif
|
|
iLLM_PASS BLOCK, %1
|
|
.6:
|
|
RET
|
|
%endmacro
|
|
|
|
INIT_XMM sse2
|
|
IDCT_SSE2 0
|
|
IDCT_SSE2 1
|
|
IDCT_SSE2 2
|