mirror of https://git.ffmpeg.org/ffmpeg.git
456 lines
13 KiB
ArmAsm
456 lines
13 KiB
ArmAsm
/*
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* Copyright © 2024 Rémi Denis-Courmont.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "libavutil/riscv/asm.S"
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.macro sx rd, addr
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#if (__riscv_xlen == 32)
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sw \rd, \addr
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#elif (__riscv_xlen == 64)
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sd \rd, \addr
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#else
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sq \rd, \addr
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#endif
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.endm
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.variant_cc ff_h264_idct4_rvv
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func ff_h264_idct4_rvv, zve32x
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vsra.vi v5, v1, 1
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vsra.vi v7, v3, 1
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vadd.vv v8, v0, v2 # z0
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vsub.vv v9, v0, v2 # z1
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vsub.vv v10, v5, v3 # z2
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vadd.vv v11, v1, v7 # z3
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vadd.vv v1, v9, v10
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vsub.vv v2, v9, v10
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vadd.vv v0, v8, v11
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vsub.vv v3, v8, v11
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jr t0
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endfunc
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func ff_h264_idct_add_8_rvv, zve32x
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csrwi vxrm, 0
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.Lidct_add4_8_rvv:
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vsetivli zero, 4, e16, mf2, ta, ma
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addi t1, a1, 1 * 4 * 2
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vle16.v v0, (a1)
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addi t2, a1, 2 * 4 * 2
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vle16.v v1, (t1)
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addi t3, a1, 3 * 4 * 2
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vle16.v v2, (t2)
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vle16.v v3, (t3)
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jal t0, ff_h264_idct4_rvv
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vse16.v v0, (a1)
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vse16.v v1, (t1)
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vse16.v v2, (t2)
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vse16.v v3, (t3)
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vlseg4e16.v v0, (a1)
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.rept 256 / __riscv_xlen
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sx zero, ((__riscv_xlen / 8) * \+)(a1)
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.endr
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jal t0, ff_h264_idct4_rvv
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add t1, a0, a2
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vle8.v v4, (a0)
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add t2, t1, a2
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vle8.v v5, (t1)
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add t3, t2, a2
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vle8.v v6, (t2)
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vle8.v v7, (t3)
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.irp n,0,1,2,3
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vssra.vi v\n, v\n, 6
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.endr
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vsetvli zero, zero, e8, mf4, ta, ma
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vwaddu.wv v0, v0, v4
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vwaddu.wv v1, v1, v5
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vwaddu.wv v2, v2, v6
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vwaddu.wv v3, v3, v7
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vsetvli zero, zero, e16, mf2, ta, ma
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.irp n,0,1,2,3
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, mf4, ta, ma
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vnclipu.wi v4, v0, 0
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vnclipu.wi v5, v1, 0
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vnclipu.wi v6, v2, 0
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vnclipu.wi v7, v3, 0
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vse8.v v4, (a0)
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vse8.v v5, (t1)
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vse8.v v6, (t2)
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vse8.v v7, (t3)
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ret
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endfunc
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.variant_cc ff_h264_idct8_rvv
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func ff_h264_idct8_rvv, zve32x
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vsra.vi v9, v7, 1
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vsra.vi v11, v3, 1
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vsra.vi v12, v2, 1
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vsra.vi v13, v5, 1
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vsra.vi v14, v6, 1
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vsra.vi v15, v1, 1
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vadd.vv v9, v3, v9
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vsub.vv v11, v1, v11
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vsub.vv v13, v13, v1
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vadd.vv v15, v3, v15
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vsub.vv v9, v5, v9
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vadd.vv v11, v11, v7
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vadd.vv v13, v13, v7
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vadd.vv v15, v15, v5
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vadd.vv v8, v0, v4 # a0
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vsub.vv v9, v9, v7 # a1
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vsub.vv v10, v0, v4 # a2
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vsub.vv v11, v11, v3 # a3
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vsub.vv v12, v12, v6 # a4
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vadd.vv v13, v13, v5 # a5
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vadd.vv v14, v14, v2 # a6
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vadd.vv v15, v15, v1 # a7
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vsra.vi v7, v9, 2
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vsra.vi v5, v11, 2
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vsra.vi v3, v13, 2
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vsra.vi v1, v15, 2
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vadd.vv v0, v8, v14 # b0
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vadd.vv v6, v10, v12 # b2
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vsub.vv v2, v10, v12 # b4
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vsub.vv v4, v8, v14 # b6
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vsub.vv v8, v15, v7 # b7
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vsub.vv v14, v5, v13 # b5
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vadd.vv v12, v1, v9 # b1
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vadd.vv v10, v11, v3 # b3
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vadd.vv v1, v6, v14
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vsub.vv v6, v6, v14
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vsub.vv v7, v0, v8
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vadd.vv v0, v0, v8
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vsub.vv v5, v2, v10
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vadd.vv v2, v2, v10
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vadd.vv v3, v4, v12
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vsub.vv v4, v4, v12
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jr t0
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endfunc
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func ff_h264_idct8_add_8_rvv, zve32x
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csrwi vxrm, 0
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.Lidct8_add_8_rvv:
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vsetivli zero, 8, e16, m1, ta, ma
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addi t1, a1, 1 * 8 * 2
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vle16.v v0, (a1)
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addi t2, a1, 2 * 8 * 2
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vle16.v v1, (t1)
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addi t3, a1, 3 * 8 * 2
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vle16.v v2, (t2)
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addi t4, a1, 4 * 8 * 2
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vle16.v v3, (t3)
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addi t5, a1, 5 * 8 * 2
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vle16.v v4, (t4)
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addi t6, a1, 6 * 8 * 2
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vle16.v v5, (t5)
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addi a7, a1, 7 * 8 * 2
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vle16.v v6, (t6)
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vle16.v v7, (a7)
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jal t0, ff_h264_idct8_rvv
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vse16.v v0, (a1)
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vse16.v v1, (t1)
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vse16.v v2, (t2)
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vse16.v v3, (t3)
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vse16.v v4, (t4)
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vse16.v v5, (t5)
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vse16.v v6, (t6)
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vse16.v v7, (a7)
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vlseg8e16.v v0, (a1)
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.rept 1024 / __riscv_xlen
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sx zero, ((__riscv_xlen / 8) * \+)(a1)
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.endr
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jal t0, ff_h264_idct8_rvv
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add t1, a0, a2
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vle8.v v16, (a0)
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add t2, t1, a2
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vle8.v v17, (t1)
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add t3, t2, a2
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vle8.v v18, (t2)
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add t4, t3, a2
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vle8.v v19, (t3)
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add t5, t4, a2
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vle8.v v20, (t4)
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add t6, t5, a2
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vle8.v v21, (t5)
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add a7, t6, a2
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vle8.v v22, (t6)
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vle8.v v23, (a7)
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.irp n,0,1,2,3,4,5,6,7
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vssra.vi v\n, v\n, 6
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.endr
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vsetvli zero, zero, e8, mf2, ta, ma
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vwaddu.wv v0, v0, v16
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vwaddu.wv v1, v1, v17
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vwaddu.wv v2, v2, v18
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vwaddu.wv v3, v3, v19
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vwaddu.wv v4, v4, v20
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vwaddu.wv v5, v5, v21
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vwaddu.wv v6, v6, v22
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vwaddu.wv v7, v7, v23
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vsetvli zero, zero, e16, m1, ta, ma
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.irp n,0,1,2,3,4,5,6,7
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, mf2, ta, ma
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vnclipu.wi v16, v0, 0
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vnclipu.wi v17, v1, 0
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vnclipu.wi v18, v2, 0
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vnclipu.wi v19, v3, 0
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vnclipu.wi v20, v4, 0
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vnclipu.wi v21, v5, 0
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vnclipu.wi v22, v6, 0
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vnclipu.wi v23, v7, 0
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vse8.v v16, (a0)
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vse8.v v17, (t1)
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vse8.v v18, (t2)
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vse8.v v19, (t3)
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vse8.v v20, (t4)
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vse8.v v21, (t5)
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vse8.v v22, (t6)
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vse8.v v23, (a7)
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ret
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endfunc
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const ff_h264_scan8
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.byte 014, 015, 024, 025, 016, 017, 026, 027
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.byte 034, 035, 044, 045, 036, 037, 046, 047
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endconst
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#if (__riscv_xlen == 64)
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.irp depth, 8
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func ff_h264_idct_add16_\depth\()_rvv, zve32x
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csrwi vxrm, 0
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addi sp, sp, -80
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lla t0, ff_h264_scan8
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sd s0, (sp)
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li t1, 32 << (\depth > 8)
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mv s0, sp
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sd ra, 8(sp)
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sd s1, 16(sp)
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sd s2, 24(sp)
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sd s3, 32(sp)
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sd s4, 40(sp)
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sd s5, 48(sp)
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sd s6, 56(sp)
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sd s7, 64(sp)
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vsetivli zero, 16, e8, m1, ta, ma
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vle8.v v8, (t0)
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vlse16.v v16, (a2), t1
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vluxei8.v v12, (a4), v8
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.if \depth == 8
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vsetvli zero, zero, e16, m2, ta, ma
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.else
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vsetvli zero, zero, e32, m4, ta, ma
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.endif
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vmsne.vi v1, v16, 0
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vsetvli zero, zero, e8, m1, ta, ma
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vmseq.vi v2, v12, 1
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vmsne.vi v0, v12, 0
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vmand.mm v1, v1, v2
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vsetvli zero, zero, e16, m2, ta, ma
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vmv.x.s s2, v0
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vmv.x.s s3, v1
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li s1, 16
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mv s4, a0
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mv s5, a1
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mv s6, a2
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mv s7, a3
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1:
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andi t0, s2, 1
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addi s1, s1, -1
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srli s2, s2, 1
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beqz t0, 3f # if (nnz)
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lw t2, (s5) # block_offset[i]
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andi t1, s3, 1
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mv a1, s6
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mv a2, s7
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add a0, s4, t2
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beqz t1, 2f # if (nnz == 1 && block[i * 16])
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call ff_h264_idct_dc_add_\depth\()_c
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j 3f
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2:
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call .Lidct_add4_\depth\()_rvv
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3:
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srli s3, s3, 1
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addi s5, s5, 4
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addi s6, s6, 16 * 2 << (\depth > 8)
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bnez s1, 1b
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ld s7, 64(sp)
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ld s6, 56(sp)
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ld s5, 48(sp)
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ld s4, 40(sp)
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ld s3, 32(sp)
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ld s2, 24(sp)
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ld s1, 16(sp)
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ld ra, 8(sp)
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ld s0, 0(sp)
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addi sp, sp, 80
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ret
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endfunc
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func ff_h264_idct_add16intra_\depth\()_rvv, zve32x
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csrwi vxrm, 0
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addi sp, sp, -80
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lla t0, ff_h264_scan8
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sd s0, (sp)
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li t1, 32 << (\depth > 8)
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mv s0, sp
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sd ra, 8(sp)
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sd s1, 16(sp)
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sd s2, 24(sp)
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sd s3, 32(sp)
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sd s4, 40(sp)
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sd s5, 48(sp)
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sd s6, 56(sp)
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sd s7, 64(sp)
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vsetivli zero, 16, e8, m1, ta, ma
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vle8.v v8, (t0)
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vlse16.v v16, (a2), t1
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vluxei8.v v12, (a4), v8
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.if \depth == 8
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vsetvli zero, zero, e16, m2, ta, ma
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.else
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vsetvli zero, zero, e32, m4, ta, ma
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.endif
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vmsne.vi v1, v16, 0
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vsetvli zero, zero, e8, m1, ta, ma
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vmsne.vi v0, v12, 0
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vsetvli zero, zero, e16, m2, ta, ma
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vmv.x.s s2, v0
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vmv.x.s s3, v1
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li s1, 16
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mv s4, a0
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mv s5, a1
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mv s6, a2
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mv s7, a3
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1:
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andi t0, s2, 1
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addi s1, s1, -1
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srli s2, s2, 1
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lw t2, (s5) # block_offset[i]
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andi t1, s3, 1
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mv a1, s6
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mv a2, s7
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add a0, s4, t2
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beqz t0, 2f # if (nnzc[scan8[i]])
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call .Lidct_add4_\depth\()_rvv
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j 3f
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2:
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beqz t1, 3f # if (block[i * 16])
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call ff_h264_idct_dc_add_\depth\()_c
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3:
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srli s3, s3, 1
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addi s5, s5, 4
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addi s6, s6, 16 * 2 << (\depth > 8)
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bnez s1, 1b
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ld s7, 64(sp)
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ld s6, 56(sp)
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ld s5, 48(sp)
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ld s4, 40(sp)
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ld s3, 32(sp)
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ld s2, 24(sp)
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ld s1, 16(sp)
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ld ra, 8(sp)
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ld s0, 0(sp)
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addi sp, sp, 80
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ret
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endfunc
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func ff_h264_idct8_add4_\depth\()_rvv, zve32x
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csrwi vxrm, 0
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addi sp, sp, -80
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lla t0, ff_h264_scan8
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sd s0, (sp)
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li t1, 4 * 32 << (\depth > 8)
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mv s0, sp
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li t2, 4
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sd ra, 8(sp)
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sd s1, 16(sp)
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sd s2, 24(sp)
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sd s3, 32(sp)
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sd s4, 40(sp)
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sd s5, 48(sp)
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sd s6, 56(sp)
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sd s7, 64(sp)
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vsetivli zero, 4, e8, mf4, ta, ma
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vlse8.v v8, (t0), t2
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vlse16.v v16, (a2), t1
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vluxei8.v v12, (a4), v8
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.if \depth == 8
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vsetvli zero, zero, e16, mf2, ta, ma
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.else
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vsetvli zero, zero, e32, m1, ta, ma
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.endif
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vmsne.vi v1, v16, 0
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vsetvli zero, zero, e8, mf4, ta, ma
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vmseq.vi v2, v12, 1
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vmsne.vi v0, v12, 0
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vmand.mm v1, v1, v2
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vmv.x.s s2, v0
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vmv.x.s s3, v1
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li s1, 4
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mv s4, a0
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mv s5, a1
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mv s6, a2
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mv s7, a3
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1:
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andi t0, s2, 1
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addi s1, s1, -1
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srli s2, s2, 1
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beqz t0, 3f # if (nnz)
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lw t2, (s5) # block_offset[i]
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andi t1, s3, 1
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mv a1, s6
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mv a2, s7
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add a0, s4, t2
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beqz t1, 2f # if (nnz == 1 && block[i * 16])
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call ff_h264_idct8_dc_add_\depth\()_c
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j 3f
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2:
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call .Lidct8_add_\depth\()_rvv
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3:
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srli s3, s3, 1
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addi s5, s5, 4 * 4
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addi s6, s6, 4 * 16 * 2 << (\depth > 8)
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bnez s1, 1b
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ld s7, 64(sp)
|
|
ld s6, 56(sp)
|
|
ld s5, 48(sp)
|
|
ld s4, 40(sp)
|
|
ld s3, 32(sp)
|
|
ld s2, 24(sp)
|
|
ld s1, 16(sp)
|
|
ld ra, 8(sp)
|
|
ld s0, 0(sp)
|
|
addi sp, sp, 80
|
|
ret
|
|
endfunc
|
|
.endr
|
|
#endif
|