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77e6293735
Use "bx lr", or "pop {lr}", which do proper mode switching
between thumb and arm modes. A plain "mov pc, lr" does not switch
from thumb mode to arm mode (while in arm mode, it does switch
mode for a thumb caller).
This is normally not an issue, as CONFIG_THUMB only is enabled if
the C compiler defaults to thumb; but stick to patterns that can
do mode switching if needed, for consistency.
Signed-off-by: Martin Storsjö <martin@martin.st>
78 lines
5.7 KiB
ArmAsm
78 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2016 Clément Bœsch <clement stupeflix.com>
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* Copyright (c) 2016 Matthieu Bouron <matthieu.bouron stupeflix.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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function ff_yuv2planeX_8_neon, export=1
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push {r4-r12, lr}
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vpush {q4-q7}
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ldr r4, [sp, #104] @ dstW
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ldr r5, [sp, #108] @ dither
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ldr r6, [sp, #112] @ offset
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vld1.8 {d0}, [r5] @ load 8x8-bit dither values
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cmp r6, #0 @ check offsetting which can be 0 or 3 only
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beq 1f
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vext.u8 d0, d0, d0, #3 @ honor offseting which can be 3 only
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1: vmovl.u8 q0, d0 @ extend dither to 16-bit
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vshll.u16 q1, d0, #12 @ extend dither to 32-bit with left shift by 12 (part 1)
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vshll.u16 q2, d1, #12 @ extend dither to 32-bit with left shift by 12 (part 2)
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mov r7, #0 @ i = 0
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2: vmov.u8 q3, q1 @ initialize accumulator with dithering values (part 1)
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vmov.u8 q4, q2 @ initialize accumulator with dithering values (part 2)
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mov r8, r1 @ tmpFilterSize = filterSize
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mov r9, r2 @ srcp
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mov r10, r0 @ filterp
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3: ldr r11, [r9], #4 @ get pointer @ src[j]
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ldr r12, [r9], #4 @ get pointer @ src[j+1]
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add r11, r11, r7, lsl #1 @ &src[j][i]
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add r12, r12, r7, lsl #1 @ &src[j+1][i]
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vld1.16 {q5}, [r11] @ read 8x16-bit @ src[j ][i + {0..7}]: A,B,C,D,E,F,G,H
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vld1.16 {q6}, [r12] @ read 8x16-bit @ src[j+1][i + {0..7}]: I,J,K,L,M,N,O,P
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ldr r11, [r10], #4 @ read 2x16-bit coeffs (X, Y) at (filter[j], filter[j+1])
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vmov.16 q7, q5 @ copy 8x16-bit @ src[j ][i + {0..7}] for following inplace zip instruction
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vmov.16 q8, q6 @ copy 8x16-bit @ src[j+1][i + {0..7}] for following inplace zip instruction
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vzip.16 q7, q8 @ A,I,B,J,C,K,D,L,E,M,F,N,G,O,H,P
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vdup.32 q15, r11 @ X,Y,X,Y,X,Y,X,Y
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vmull.s16 q9, d14, d30 @ A*X,I*Y,B*X,J*Y
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vmull.s16 q10, d15, d31 @ C*X,K*Y,D*X,L*Y
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vmull.s16 q11, d16, d30 @ E*X,M*Y,F*X,N*Y
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vmull.s16 q12, d17, d31 @ G*X,O*Y,H*X,P*Y
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vpadd.s32 d10, d18, d19 @ A*X+I*Y,B*X+J*Y
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vpadd.s32 d11, d20, d21 @ C*X+K*Y,D*X+L*Y
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vpadd.s32 d12, d22, d23 @ E*X+M*Y,F*X+N*Y
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vpadd.s32 d13, d24, d25 @ G*X+O*Y,H*X+P*Y
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vadd.s32 q3, q5 @ update val accumulator (part 1)
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vadd.s32 q4, q6 @ update val accumulator (part 2)
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subs r8, #2 @ tmpFilterSize -= 2
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bgt 3b @ loop until filterSize is consumed
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vshr.s32 q3, q3, #19 @ val>>19 (part 1)
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vshr.s32 q4, q4, #19 @ val>>19 (part 2)
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vqmovun.s32 d6, q3 @ clip16(val>>19) (part 1)
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vqmovun.s32 d7, q4 @ clip16(val>>19) (part 2)
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vqmovn.u16 d6, q3 @ merge part 1 and part 2
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vst1.8 {d6}, [r3]! @ write destination
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add r7, #8 @ i += 8
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subs r4, r4, #8 @ dstW -= 8
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bgt 2b @ loop until width is consumed
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vpop {q4-q7}
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pop {r4-r12, pc}
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endfunc
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