mirror of https://git.ffmpeg.org/ffmpeg.git
487 lines
24 KiB
C
487 lines
24 KiB
C
/*
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* VC-1 and WMV3 - DSP functions MMX-optimized
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* Copyright (c) 2007 Christophe GISQUET <christophe.gisquet@free.fr>
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "libavutil/cpu.h"
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#include "libavutil/mem.h"
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#include "libavutil/x86/asm.h"
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#include "libavutil/x86/cpu.h"
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#include "libavcodec/vc1dsp.h"
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#include "constants.h"
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#include "fpel.h"
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#include "vc1dsp.h"
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#if HAVE_6REGS && HAVE_INLINE_ASM && HAVE_MMX_EXTERNAL
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void ff_vc1_put_ver_16b_shift2_mmx(int16_t *dst,
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const uint8_t *src, x86_reg stride,
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int rnd, int64_t shift);
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void ff_vc1_put_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,
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const int16_t *src, int rnd);
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void ff_vc1_avg_hor_16b_shift2_mmxext(uint8_t *dst, x86_reg stride,
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const int16_t *src, int rnd);
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#define OP_PUT(S,D)
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#define OP_AVG(S,D) "pavgb " #S ", " #D " \n\t"
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/** Add rounder from mm7 to mm3 and pack result at destination */
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#define NORMALIZE_MMX(SHIFT) \
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"paddw %%mm7, %%mm3 \n\t" /* +bias-r */ \
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"paddw %%mm7, %%mm4 \n\t" /* +bias-r */ \
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"psraw "SHIFT", %%mm3 \n\t" \
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"psraw "SHIFT", %%mm4 \n\t"
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#define TRANSFER_DO_PACK(OP) \
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"packuswb %%mm4, %%mm3 \n\t" \
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OP((%2), %%mm3) \
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"movq %%mm3, (%2) \n\t"
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#define TRANSFER_DONT_PACK(OP) \
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OP(0(%2), %%mm3) \
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OP(8(%2), %%mm4) \
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"movq %%mm3, 0(%2) \n\t" \
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"movq %%mm4, 8(%2) \n\t"
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/** @see MSPEL_FILTER13_CORE for use as UNPACK macro */
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#define DO_UNPACK(reg) "punpcklbw %%mm0, " reg "\n\t"
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#define DONT_UNPACK(reg)
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/** Compute the rounder 32-r or 8-r and unpacks it to mm7 */
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#define LOAD_ROUNDER_MMX(ROUND) \
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"movd "ROUND", %%mm7 \n\t" \
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"punpcklwd %%mm7, %%mm7 \n\t" \
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"punpckldq %%mm7, %%mm7 \n\t"
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/**
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* Purely vertical or horizontal 1/2 shift interpolation.
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* Sacrifice mm6 for *9 factor.
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*/
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#define VC1_SHIFT2(OP, OPNAME)\
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static void OPNAME ## vc1_shift2_mmx(uint8_t *dst, const uint8_t *src,\
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x86_reg stride, int rnd, x86_reg offset)\
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{\
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rnd = 8-rnd;\
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__asm__ volatile(\
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"mov $8, %%"FF_REG_c" \n\t"\
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LOAD_ROUNDER_MMX("%5")\
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"movq "MANGLE(ff_pw_9)", %%mm6\n\t"\
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"1: \n\t"\
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"movd 0(%0 ), %%mm3 \n\t"\
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"movd 4(%0 ), %%mm4 \n\t"\
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"movd 0(%0,%2), %%mm1 \n\t"\
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"movd 4(%0,%2), %%mm2 \n\t"\
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"add %2, %0 \n\t"\
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"punpcklbw %%mm0, %%mm3 \n\t"\
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"punpcklbw %%mm0, %%mm4 \n\t"\
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"punpcklbw %%mm0, %%mm1 \n\t"\
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"punpcklbw %%mm0, %%mm2 \n\t"\
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"paddw %%mm1, %%mm3 \n\t"\
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"paddw %%mm2, %%mm4 \n\t"\
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"movd 0(%0,%3), %%mm1 \n\t"\
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"movd 4(%0,%3), %%mm2 \n\t"\
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"pmullw %%mm6, %%mm3 \n\t" /* 0,9,9,0*/\
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"pmullw %%mm6, %%mm4 \n\t" /* 0,9,9,0*/\
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"punpcklbw %%mm0, %%mm1 \n\t"\
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"punpcklbw %%mm0, %%mm2 \n\t"\
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"psubw %%mm1, %%mm3 \n\t" /*-1,9,9,0*/\
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"psubw %%mm2, %%mm4 \n\t" /*-1,9,9,0*/\
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"movd 0(%0,%2), %%mm1 \n\t"\
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"movd 4(%0,%2), %%mm2 \n\t"\
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"punpcklbw %%mm0, %%mm1 \n\t"\
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"punpcklbw %%mm0, %%mm2 \n\t"\
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"psubw %%mm1, %%mm3 \n\t" /*-1,9,9,-1*/\
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"psubw %%mm2, %%mm4 \n\t" /*-1,9,9,-1*/\
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NORMALIZE_MMX("$4")\
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"packuswb %%mm4, %%mm3 \n\t"\
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OP((%1), %%mm3)\
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"movq %%mm3, (%1) \n\t"\
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"add %6, %0 \n\t"\
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"add %4, %1 \n\t"\
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"dec %%"FF_REG_c" \n\t"\
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"jnz 1b \n\t"\
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: "+r"(src), "+r"(dst)\
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: "r"(offset), "r"(-2*offset), "g"(stride), "m"(rnd),\
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"g"(stride-offset)\
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NAMED_CONSTRAINTS_ADD(ff_pw_9)\
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: "%"FF_REG_c, "memory"\
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);\
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}
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VC1_SHIFT2(OP_PUT, put_)
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VC1_SHIFT2(OP_AVG, avg_)
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/**
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* Core of the 1/4 and 3/4 shift bicubic interpolation.
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*
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* @param UNPACK Macro unpacking arguments from 8 to 16 bits (can be empty).
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* @param MOVQ "movd 1" or "movq 2", if data read is already unpacked.
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* @param A1 Address of 1st tap (beware of unpacked/packed).
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* @param A2 Address of 2nd tap
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* @param A3 Address of 3rd tap
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* @param A4 Address of 4th tap
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*/
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#define MSPEL_FILTER13_CORE(UNPACK, MOVQ, A1, A2, A3, A4) \
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MOVQ "*0+"A1", %%mm1 \n\t" \
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MOVQ "*4+"A1", %%mm2 \n\t" \
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UNPACK("%%mm1") \
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UNPACK("%%mm2") \
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"pmullw "MANGLE(ff_pw_3)", %%mm1\n\t" \
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"pmullw "MANGLE(ff_pw_3)", %%mm2\n\t" \
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MOVQ "*0+"A2", %%mm3 \n\t" \
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MOVQ "*4+"A2", %%mm4 \n\t" \
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UNPACK("%%mm3") \
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UNPACK("%%mm4") \
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"pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
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"pmullw %%mm6, %%mm4 \n\t" /* *18 */ \
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"psubw %%mm1, %%mm3 \n\t" /* 18,-3 */ \
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"psubw %%mm2, %%mm4 \n\t" /* 18,-3 */ \
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MOVQ "*0+"A4", %%mm1 \n\t" \
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MOVQ "*4+"A4", %%mm2 \n\t" \
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UNPACK("%%mm1") \
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UNPACK("%%mm2") \
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"psllw $2, %%mm1 \n\t" /* 4* */ \
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"psllw $2, %%mm2 \n\t" /* 4* */ \
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"psubw %%mm1, %%mm3 \n\t" /* -4,18,-3 */ \
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"psubw %%mm2, %%mm4 \n\t" /* -4,18,-3 */ \
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MOVQ "*0+"A3", %%mm1 \n\t" \
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MOVQ "*4+"A3", %%mm2 \n\t" \
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UNPACK("%%mm1") \
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UNPACK("%%mm2") \
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"pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
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"pmullw %%mm5, %%mm2 \n\t" /* *53 */ \
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"paddw %%mm1, %%mm3 \n\t" /* 4,53,18,-3 */ \
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"paddw %%mm2, %%mm4 \n\t" /* 4,53,18,-3 */
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/**
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* Macro to build the vertical 16 bits version of vc1_put_shift[13].
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* Here, offset=src_stride. Parameters passed A1 to A4 must use
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* %3 (src_stride) and %4 (3*src_stride).
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*
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* @param NAME Either 1 or 3
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* @see MSPEL_FILTER13_CORE for information on A1->A4
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*/
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#define MSPEL_FILTER13_VER_16B(NAME, A1, A2, A3, A4) \
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static void \
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vc1_put_ver_16b_ ## NAME ## _mmx(int16_t *dst, const uint8_t *src, \
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x86_reg src_stride, \
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int rnd, int64_t shift) \
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{ \
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int h = 8; \
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src -= src_stride; \
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__asm__ volatile( \
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LOAD_ROUNDER_MMX("%5") \
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"movq "MANGLE(ff_pw_53)", %%mm5\n\t" \
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"movq "MANGLE(ff_pw_18)", %%mm6\n\t" \
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".p2align 3 \n\t" \
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"1: \n\t" \
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MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4) \
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NORMALIZE_MMX("%6") \
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TRANSFER_DONT_PACK(OP_PUT) \
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/* Last 3 (in fact 4) bytes on the line */ \
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"movd 8+"A1", %%mm1 \n\t" \
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DO_UNPACK("%%mm1") \
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"movq %%mm1, %%mm3 \n\t" \
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"paddw %%mm1, %%mm1 \n\t" \
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"paddw %%mm3, %%mm1 \n\t" /* 3* */ \
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"movd 8+"A2", %%mm3 \n\t" \
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DO_UNPACK("%%mm3") \
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"pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
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"psubw %%mm1, %%mm3 \n\t" /*18,-3 */ \
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"movd 8+"A3", %%mm1 \n\t" \
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DO_UNPACK("%%mm1") \
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"pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
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"paddw %%mm1, %%mm3 \n\t" /*53,18,-3 */ \
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"movd 8+"A4", %%mm1 \n\t" \
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DO_UNPACK("%%mm1") \
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"psllw $2, %%mm1 \n\t" /* 4* */ \
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"psubw %%mm1, %%mm3 \n\t" \
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"paddw %%mm7, %%mm3 \n\t" \
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"psraw %6, %%mm3 \n\t" \
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"movq %%mm3, 16(%2) \n\t" \
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"add %3, %1 \n\t" \
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"add $24, %2 \n\t" \
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"decl %0 \n\t" \
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"jnz 1b \n\t" \
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: "+r"(h), "+r" (src), "+r" (dst) \
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: "r"(src_stride), "r"(3*src_stride), \
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"m"(rnd), "m"(shift) \
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NAMED_CONSTRAINTS_ADD(ff_pw_3,ff_pw_53,ff_pw_18) \
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: "memory" \
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); \
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}
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/**
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* Macro to build the horizontal 16 bits version of vc1_put_shift[13].
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* Here, offset=16 bits, so parameters passed A1 to A4 should be simple.
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*
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* @param NAME Either 1 or 3
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* @see MSPEL_FILTER13_CORE for information on A1->A4
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*/
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#define MSPEL_FILTER13_HOR_16B(NAME, A1, A2, A3, A4, OP, OPNAME) \
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static void \
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OPNAME ## vc1_hor_16b_ ## NAME ## _mmx(uint8_t *dst, x86_reg stride, \
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const int16_t *src, int rnd) \
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{ \
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int h = 8; \
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src -= 1; \
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rnd -= (-4+58+13-3)*256; /* Add -256 bias */ \
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__asm__ volatile( \
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LOAD_ROUNDER_MMX("%4") \
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"movq "MANGLE(ff_pw_18)", %%mm6 \n\t" \
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"movq "MANGLE(ff_pw_53)", %%mm5 \n\t" \
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".p2align 3 \n\t" \
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"1: \n\t" \
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MSPEL_FILTER13_CORE(DONT_UNPACK, "movq 2", A1, A2, A3, A4) \
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NORMALIZE_MMX("$7") \
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/* Remove bias */ \
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"paddw "MANGLE(ff_pw_128)", %%mm3 \n\t" \
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"paddw "MANGLE(ff_pw_128)", %%mm4 \n\t" \
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TRANSFER_DO_PACK(OP) \
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"add $24, %1 \n\t" \
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"add %3, %2 \n\t" \
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"decl %0 \n\t" \
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"jnz 1b \n\t" \
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: "+r"(h), "+r" (src), "+r" (dst) \
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: "r"(stride), "m"(rnd) \
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NAMED_CONSTRAINTS_ADD(ff_pw_3,ff_pw_18,ff_pw_53,ff_pw_128) \
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: "memory" \
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); \
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}
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/**
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* Macro to build the 8 bits, any direction, version of vc1_put_shift[13].
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* Here, offset=src_stride. Parameters passed A1 to A4 must use
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* %3 (offset) and %4 (3*offset).
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*
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* @param NAME Either 1 or 3
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* @see MSPEL_FILTER13_CORE for information on A1->A4
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*/
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#define MSPEL_FILTER13_8B(NAME, A1, A2, A3, A4, OP, OPNAME) \
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static void \
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OPNAME ## vc1_## NAME ## _mmx(uint8_t *dst, const uint8_t *src, \
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x86_reg stride, int rnd, x86_reg offset) \
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{ \
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int h = 8; \
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src -= offset; \
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rnd = 32-rnd; \
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__asm__ volatile ( \
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LOAD_ROUNDER_MMX("%6") \
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"movq "MANGLE(ff_pw_53)", %%mm5 \n\t" \
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"movq "MANGLE(ff_pw_18)", %%mm6 \n\t" \
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".p2align 3 \n\t" \
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"1: \n\t" \
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MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4) \
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NORMALIZE_MMX("$6") \
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TRANSFER_DO_PACK(OP) \
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"add %5, %1 \n\t" \
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"add %5, %2 \n\t" \
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"decl %0 \n\t" \
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"jnz 1b \n\t" \
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: "+r"(h), "+r" (src), "+r" (dst) \
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: "r"(offset), "r"(3*offset), "g"(stride), "m"(rnd) \
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NAMED_CONSTRAINTS_ADD(ff_pw_53,ff_pw_18,ff_pw_3) \
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: "memory" \
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); \
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}
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/** 1/4 shift bicubic interpolation */
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MSPEL_FILTER13_8B (shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )", OP_PUT, put_)
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MSPEL_FILTER13_8B (shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )", OP_AVG, avg_)
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MSPEL_FILTER13_VER_16B(shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )")
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MSPEL_FILTER13_HOR_16B(shift1, "2*3(%1)", "2*2(%1)", "2*1(%1)", "2*0(%1)", OP_PUT, put_)
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MSPEL_FILTER13_HOR_16B(shift1, "2*3(%1)", "2*2(%1)", "2*1(%1)", "2*0(%1)", OP_AVG, avg_)
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/** 3/4 shift bicubic interpolation */
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MSPEL_FILTER13_8B (shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )", OP_PUT, put_)
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MSPEL_FILTER13_8B (shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )", OP_AVG, avg_)
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MSPEL_FILTER13_VER_16B(shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )")
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MSPEL_FILTER13_HOR_16B(shift3, "2*0(%1)", "2*1(%1)", "2*2(%1)", "2*3(%1)", OP_PUT, put_)
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MSPEL_FILTER13_HOR_16B(shift3, "2*0(%1)", "2*1(%1)", "2*2(%1)", "2*3(%1)", OP_AVG, avg_)
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typedef void (*vc1_mspel_mc_filter_ver_16bits)(int16_t *dst, const uint8_t *src, x86_reg src_stride, int rnd, int64_t shift);
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typedef void (*vc1_mspel_mc_filter_hor_16bits)(uint8_t *dst, x86_reg dst_stride, const int16_t *src, int rnd);
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typedef void (*vc1_mspel_mc_filter_8bits)(uint8_t *dst, const uint8_t *src, x86_reg stride, int rnd, x86_reg offset);
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/**
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* Interpolate fractional pel values by applying proper vertical then
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* horizontal filter.
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*
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* @param dst Destination buffer for interpolated pels.
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* @param src Source buffer.
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* @param stride Stride for both src and dst buffers.
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* @param hmode Horizontal filter (expressed in quarter pixels shift).
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* @param hmode Vertical filter.
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* @param rnd Rounding bias.
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*/
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#define VC1_MSPEL_MC(OP, INSTR)\
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static void OP ## vc1_mspel_mc(uint8_t *dst, const uint8_t *src, int stride,\
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int hmode, int vmode, int rnd)\
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{\
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static const vc1_mspel_mc_filter_ver_16bits vc1_put_shift_ver_16bits[] =\
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{ NULL, vc1_put_ver_16b_shift1_mmx, ff_vc1_put_ver_16b_shift2_mmx, vc1_put_ver_16b_shift3_mmx };\
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static const vc1_mspel_mc_filter_hor_16bits vc1_put_shift_hor_16bits[] =\
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{ NULL, OP ## vc1_hor_16b_shift1_mmx, ff_vc1_ ## OP ## hor_16b_shift2_ ## INSTR, OP ## vc1_hor_16b_shift3_mmx };\
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static const vc1_mspel_mc_filter_8bits vc1_put_shift_8bits[] =\
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{ NULL, OP ## vc1_shift1_mmx, OP ## vc1_shift2_mmx, OP ## vc1_shift3_mmx };\
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\
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__asm__ volatile(\
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"pxor %%mm0, %%mm0 \n\t"\
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::: "memory"\
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);\
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\
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if (vmode) { /* Vertical filter to apply */\
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if (hmode) { /* Horizontal filter to apply, output to tmp */\
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static const int shift_value[] = { 0, 5, 1, 5 };\
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int shift = (shift_value[hmode]+shift_value[vmode])>>1;\
|
|
int r;\
|
|
LOCAL_ALIGNED(16, int16_t, tmp, [12*8]);\
|
|
\
|
|
r = (1<<(shift-1)) + rnd-1;\
|
|
vc1_put_shift_ver_16bits[vmode](tmp, src-1, stride, r, shift);\
|
|
\
|
|
vc1_put_shift_hor_16bits[hmode](dst, stride, tmp+1, 64-rnd);\
|
|
return;\
|
|
}\
|
|
else { /* No horizontal filter, output 8 lines to dst */\
|
|
vc1_put_shift_8bits[vmode](dst, src, stride, 1-rnd, stride);\
|
|
return;\
|
|
}\
|
|
}\
|
|
\
|
|
/* Horizontal mode with no vertical mode */\
|
|
vc1_put_shift_8bits[hmode](dst, src, stride, rnd, 1);\
|
|
} \
|
|
static void OP ## vc1_mspel_mc_16(uint8_t *dst, const uint8_t *src, \
|
|
int stride, int hmode, int vmode, int rnd)\
|
|
{ \
|
|
OP ## vc1_mspel_mc(dst + 0, src + 0, stride, hmode, vmode, rnd); \
|
|
OP ## vc1_mspel_mc(dst + 8, src + 8, stride, hmode, vmode, rnd); \
|
|
dst += 8*stride; src += 8*stride; \
|
|
OP ## vc1_mspel_mc(dst + 0, src + 0, stride, hmode, vmode, rnd); \
|
|
OP ## vc1_mspel_mc(dst + 8, src + 8, stride, hmode, vmode, rnd); \
|
|
}
|
|
|
|
VC1_MSPEL_MC(put_, mmx)
|
|
VC1_MSPEL_MC(avg_, mmxext)
|
|
|
|
/** Macro to ease bicubic filter interpolation functions declarations */
|
|
#define DECLARE_FUNCTION(a, b) \
|
|
static void put_vc1_mspel_mc ## a ## b ## _mmx(uint8_t *dst, \
|
|
const uint8_t *src, \
|
|
ptrdiff_t stride, \
|
|
int rnd) \
|
|
{ \
|
|
put_vc1_mspel_mc(dst, src, stride, a, b, rnd); \
|
|
}\
|
|
static void avg_vc1_mspel_mc ## a ## b ## _mmxext(uint8_t *dst, \
|
|
const uint8_t *src, \
|
|
ptrdiff_t stride, \
|
|
int rnd) \
|
|
{ \
|
|
avg_vc1_mspel_mc(dst, src, stride, a, b, rnd); \
|
|
}\
|
|
static void put_vc1_mspel_mc ## a ## b ## _16_mmx(uint8_t *dst, \
|
|
const uint8_t *src, \
|
|
ptrdiff_t stride, \
|
|
int rnd) \
|
|
{ \
|
|
put_vc1_mspel_mc_16(dst, src, stride, a, b, rnd); \
|
|
}\
|
|
static void avg_vc1_mspel_mc ## a ## b ## _16_mmxext(uint8_t *dst, \
|
|
const uint8_t *src,\
|
|
ptrdiff_t stride, \
|
|
int rnd) \
|
|
{ \
|
|
avg_vc1_mspel_mc_16(dst, src, stride, a, b, rnd); \
|
|
}
|
|
|
|
DECLARE_FUNCTION(0, 1)
|
|
DECLARE_FUNCTION(0, 2)
|
|
DECLARE_FUNCTION(0, 3)
|
|
|
|
DECLARE_FUNCTION(1, 0)
|
|
DECLARE_FUNCTION(1, 1)
|
|
DECLARE_FUNCTION(1, 2)
|
|
DECLARE_FUNCTION(1, 3)
|
|
|
|
DECLARE_FUNCTION(2, 0)
|
|
DECLARE_FUNCTION(2, 1)
|
|
DECLARE_FUNCTION(2, 2)
|
|
DECLARE_FUNCTION(2, 3)
|
|
|
|
DECLARE_FUNCTION(3, 0)
|
|
DECLARE_FUNCTION(3, 1)
|
|
DECLARE_FUNCTION(3, 2)
|
|
DECLARE_FUNCTION(3, 3)
|
|
|
|
#define FN_ASSIGN(OP, X, Y, INSN) \
|
|
dsp->OP##vc1_mspel_pixels_tab[1][X+4*Y] = OP##vc1_mspel_mc##X##Y##INSN; \
|
|
dsp->OP##vc1_mspel_pixels_tab[0][X+4*Y] = OP##vc1_mspel_mc##X##Y##_16##INSN
|
|
|
|
av_cold void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
|
|
{
|
|
FN_ASSIGN(put_, 0, 1, _mmx);
|
|
FN_ASSIGN(put_, 0, 2, _mmx);
|
|
FN_ASSIGN(put_, 0, 3, _mmx);
|
|
|
|
FN_ASSIGN(put_, 1, 0, _mmx);
|
|
FN_ASSIGN(put_, 1, 1, _mmx);
|
|
FN_ASSIGN(put_, 1, 2, _mmx);
|
|
FN_ASSIGN(put_, 1, 3, _mmx);
|
|
|
|
FN_ASSIGN(put_, 2, 0, _mmx);
|
|
FN_ASSIGN(put_, 2, 1, _mmx);
|
|
FN_ASSIGN(put_, 2, 2, _mmx);
|
|
FN_ASSIGN(put_, 2, 3, _mmx);
|
|
|
|
FN_ASSIGN(put_, 3, 0, _mmx);
|
|
FN_ASSIGN(put_, 3, 1, _mmx);
|
|
FN_ASSIGN(put_, 3, 2, _mmx);
|
|
FN_ASSIGN(put_, 3, 3, _mmx);
|
|
}
|
|
|
|
av_cold void ff_vc1dsp_init_mmxext(VC1DSPContext *dsp)
|
|
{
|
|
FN_ASSIGN(avg_, 0, 1, _mmxext);
|
|
FN_ASSIGN(avg_, 0, 2, _mmxext);
|
|
FN_ASSIGN(avg_, 0, 3, _mmxext);
|
|
|
|
FN_ASSIGN(avg_, 1, 0, _mmxext);
|
|
FN_ASSIGN(avg_, 1, 1, _mmxext);
|
|
FN_ASSIGN(avg_, 1, 2, _mmxext);
|
|
FN_ASSIGN(avg_, 1, 3, _mmxext);
|
|
|
|
FN_ASSIGN(avg_, 2, 0, _mmxext);
|
|
FN_ASSIGN(avg_, 2, 1, _mmxext);
|
|
FN_ASSIGN(avg_, 2, 2, _mmxext);
|
|
FN_ASSIGN(avg_, 2, 3, _mmxext);
|
|
|
|
FN_ASSIGN(avg_, 3, 0, _mmxext);
|
|
FN_ASSIGN(avg_, 3, 1, _mmxext);
|
|
FN_ASSIGN(avg_, 3, 2, _mmxext);
|
|
FN_ASSIGN(avg_, 3, 3, _mmxext);
|
|
}
|
|
#endif /* HAVE_6REGS && HAVE_INLINE_ASM && HAVE_MMX_EXTERNAL */
|