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5b170c0bea
GCC 4.3 and later do the right thing with the plain C code. Earlier versions in 32-bit mode generate one extra instruction, needlessly zeroing what would be the high half of the shifted value. At least two gcc configurations miscompile the inline asm in some situations. In 64-bit mode, all gcc versions generate imul r64, r64 followed by shr. On Intel i7 and later, this imul is faster 32-bit mul. On older Intel and all AMD, it is slightly slower. On Atom it is much slower. Considering where the FASTDIV macro is used, any overall negative performance impact of this change should be negligible. If anyone cares, they should file a bug against gcc and get the instruction selection fixed. Signed-off-by: Mans Rullgard <mans@mansr.com> |
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| .. | ||
| asm.h | ||
| bswap.h | ||
| cpu.c | ||
| float_dsp_init.c | ||
| float_dsp.asm | ||
| intreadwrite.h | ||
| Makefile | ||
| timer.h | ||
| w64xmmtest.h | ||
| x86inc.asm | ||
| x86util.asm | ||