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cc86343b96
Building iOS platform with arm64, the compiler has a warning: "instruction movi.2d with immediate #0 may not function correctly on this CPU, converting to movi.16b" Signed-off-by: xufuji456 <839789740@qq.com> Signed-off-by: Martin Storsjö <martin@martin.st>
226 lines
7.3 KiB
ArmAsm
226 lines
7.3 KiB
ArmAsm
/*
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* Copyright (c) 2014 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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#define FRAC_BITS 23 // fractional bits for sb_samples and dct
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#define WFRAC_BITS 16 // fractional bits for window
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#define OUT_SHIFT (WFRAC_BITS + FRAC_BITS - 15)
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const tbl_rev128_s, align=4
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.byte 12, 13, 14, 15
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.byte 8, 9, 10, 11
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.byte 4, 5, 6, 7
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.byte 0, 1, 2, 3
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endconst
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.macro apply_window type, st
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function ff_mpadsp_apply_window_\type\()_neon, export=1
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mov x7, x0
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add x8, x0, #512<<2
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ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x7], #64
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x7], #64
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st1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x8], #64
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st1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x8], #64
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movrel x15, tbl_rev128_s
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ld1 {v27.4s}, [x15]
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.ifc \type, fixed
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lsl x4, x4, #1
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.else
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lsl x4, x4, #2
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.endif
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add x10, x0, #45<<2
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add x0, x0, #16<<2
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add x1, x1, #16<<2
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add x5, x3, x4, lsl #5
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sub x5, x5, x4 // samples2
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neg x13, x4 // -incr
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mov x9, #64<<2
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.ifc \type, fixed
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ld1r {v16.2s}, [x2] // dither_state
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sxtl v16.2d, v16.2s
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movi v29.16b, #0
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movi v30.2d, #(1<<OUT_SHIFT)-1
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trn1 v31.2d, v29.2d, v30.2d
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trn2 v30.2d, v30.2d, v29.2d
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trn1 v16.2d, v16.2d, v29.2d
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.else
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movi v16.4s, #0
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movi v28.4s, #0
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.endif
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mov x14, #4
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1:
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mov x8, x0
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sub x7, x1, #3<<2
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sub x6, x1, x14, lsl #4
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add x7, x7, x14, lsl #4
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add x11, x6, #(32)<<2 // w + 32
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add x12, x7, #(32)<<2 // w2 + 32
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mov x15, #8
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movi v17.16b, #0
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movi v18.16b, #0
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movi v19.16b, #0
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2:
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subs x15, x15, #1
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ld1 {v0.4s}, [x8], x9
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ld1 {v1.4s}, [x10], x9
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ld1 {v2.4s}, [x6], x9
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ld1 {v3.4s}, [x7], x9
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tbl v6.16b, {v0.16b}, v27.16b
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tbl v7.16b, {v1.16b}, v27.16b
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ld1 {v4.4s}, [x11], x9
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ld1 {v5.4s}, [x12], x9
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MLA v16, v2, v0
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MLA2 v17, v2, v0
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MLS v18, v3, v6
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MLS2 v19, v3, v6
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MLS v16, v4, v7
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MLS2 v17, v4, v7
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MLS v18, v5, v1
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MLS2 v19, v5, v1
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b.gt 2b
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cmp x14, #4
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sub x10, x10, #64<<5 // 64 * 8 * sizeof(int32_t)
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.ifc \type, fixed
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and v28.16b, v16.16b, v30.16b
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ext v28.16b, v29.16b, v28.16b, #8
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b.eq 4f
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round_sample v19, 1, 1
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4:
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round_sample v16, 1, 0
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shrn v16.2s, v16.2d, #OUT_SHIFT
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round_sample v19, 0, 0
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shrn v19.2s, v19.2d, #OUT_SHIFT
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round_sample v17, 0, 1
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round_sample v18, 1, 1
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round_sample v17, 1, 0
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shrn2 v16.4s, v17.2d, #OUT_SHIFT
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round_sample v18, 0, 0
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shrn2 v19.4s, v18.2d, #OUT_SHIFT
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sqxtn v16.4h, v16.4s
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sqxtn v18.4h, v19.4s
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.else
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ext v18.16b, v18.16b, v18.16b, #8
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.endif
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st1 {v16.\st\()}[0], [x3], x4
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b.eq 4f
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st1 {v18.\st\()}[1], [x5], x13
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4:
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st1 {v16.\st\()}[1], [x3], x4
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st1 {v18.\st\()}[0], [x5], x13
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st1 {v16.\st\()}[2], [x3], x4
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st1 {v18.\st\()}[3], [x5], x13
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st1 {v16.\st\()}[3], [x3], x4
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st1 {v18.\st\()}[2], [x5], x13
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mov v16.16b, v28.16b
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subs x14, x14, #1
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add x0, x0, #4<<2
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sub x10, x10, #4<<2
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b.gt 1b
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// computing samples[16]
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add x6, x1, #32<<2
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ld1 {v0.2s}, [x6], x9
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ld1 {v1.2s}, [x0], x9
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.rept 3
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ld1 {v2.2s}, [x6], x9
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ld1 {v3.2s}, [x0], x9
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MLS v16, v0, v1
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ld1 {v0.2s}, [x6], x9
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ld1 {v1.2s}, [x0], x9
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MLS v16, v2, v3
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.endr
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ld1 {v2.2s}, [x6], x9
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ld1 {v3.2s}, [x0], x9
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MLS v16, v0, v1
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MLS v16, v2, v3
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.ifc \type, fixed
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and v28.16b, v16.16b, v30.16b
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shrn v20.2s, v16.2d, #OUT_SHIFT
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xtn v28.2s, v28.2d
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sqxtn v20.4h, v20.4s
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st1 {v28.s}[0], [x2] // save dither_state
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st1 {v20.h}[0], [x3]
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.else
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st1 {v16.s}[0], [x3]
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.endif
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ret
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endfunc
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.purgem round_sample
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.purgem MLA
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.purgem MLA2
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.purgem MLS
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.purgem MLS2
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.endm
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.macro round_sample r, idx, next
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add \r\().2d, \r\().2d, v28.2d
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.if \idx == 0
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and v28.16b, \r\().16b, v30.16b
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.else // \idx == 1
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and v28.16b, \r\().16b, v31.16b
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.endif
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.if \idx != \next
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.if \next == 0
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ext v28.16b, v28.16b, v29.16b, #8
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.else
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ext v28.16b, v29.16b, v28.16b, #8
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.endif
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.endif
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.endm
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.macro MLA d, s1, s2
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smlal \d\().2d, \s1\().2s, \s2\().2s
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.endm
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.macro MLA2 d, s1, s2
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smlal2 \d\().2d, \s1\().4s, \s2\().4s
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.endm
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.macro MLS d, s1, s2
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smlsl \d\().2d, \s1\().2s, \s2\().2s
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.endm
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.macro MLS2 d, s1, s2
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smlsl2 \d\().2d, \s1\().4s, \s2\().4s
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.endm
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apply_window fixed, h
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// nothing to do for round_sample and ML{A,S}2
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.macro round_sample r, idx, next
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.endm
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.macro MLA2 d, s1, s2
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.endm
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.macro MLS2 d, s1, s2
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.endm
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.macro MLA d, s1, s2
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fmla \d\().4s, \s1\().4s, \s2\().4s
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.endm
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.macro MLS d, s1, s2
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fmls \d\().4s, \s1\().4s, \s2\().4s
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.endm
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apply_window float, s
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