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6d60cc7baf
In my personal opinion, we should not need to support unaligned YUY2 pixel maps. They should always be aligned to at least 32 bits, and the current code assumes just 16 bits. However checkasm does test for unaligned input bitmaps. QEMU accepts it, but real hardware dose not. In this particular case, we can at the same time improve performance and handle unaligned inputs, so do just that. uyvytoyuv422_c: 104379.0 uyvytoyuv422_c: 104060.0 uyvytoyuv422_rvv_i32: 25284.0 (before) uyvytoyuv422_rvv_i32: 19303.2 (after)
175 lines
4.2 KiB
ArmAsm
175 lines
4.2 KiB
ArmAsm
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_shuffle_bytes_0321_rvv, zve32x
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li t1, 0x00ff00ff
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j 1f
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endfunc
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func ff_shuffle_bytes_2103_rvv, zve32x
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li t1, ~0x00ff00ff
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1:
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not t2, t1
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srai a2, a2, 2
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2:
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vsetvli t0, a2, e32, m8, ta, ma
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vle32.v v8, (a0)
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sub a2, a2, t0
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vand.vx v16, v8, t2
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sh2add a0, t0, a0
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vand.vx v8, v8, t1
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vsrl.vi v24, v16, 16
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vsll.vi v16, v16, 16
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vor.vv v8, v8, v24
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vor.vv v8, v16, v8
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vse32.v v8, (a1)
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sh2add a1, t0, a1
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bnez a2, 2b
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ret
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endfunc
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func ff_shuffle_bytes_1230_rvv, zve32x
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li t1, 24
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li t2, 8
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j 3f
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endfunc
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func ff_shuffle_bytes_3012_rvv, zve32x
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li t1, 8
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li t2, 24
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3:
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srai a2, a2, 2
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4:
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vsetvli t0, a2, e32, m8, ta, ma
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vle32.v v8, (a0)
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sub a2, a2, t0
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vsll.vx v16, v8, t1
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sh2add a0, t0, a0
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vsrl.vx v8, v8, t2
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vor.vv v16, v16, v8
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vse32.v v16, (a1)
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sh2add a1, t0, a1
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bnez a2, 4b
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ret
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endfunc
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func ff_interleave_bytes_rvv, zve32x
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1:
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mv t0, a0
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mv t1, a1
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mv t2, a2
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mv t3, a3
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addi a4, a4, -1
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2:
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vsetvli t4, t3, e8, m4, ta, ma
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sub t3, t3, t4
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vle8.v v8, (t0)
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add t0, t4, t0
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vle8.v v12, (t1)
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add t1, t4, t1
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vsseg2e8.v v8, (t2)
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sh1add t2, t4, t2
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bnez t3, 2b
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add a0, a0, a5
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add a1, a1, a6
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add a2, a2, a7
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bnez a4, 1b
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ret
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endfunc
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func ff_deinterleave_bytes_rvv, zve32x
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1:
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mv t0, a0
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mv t1, a1
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mv t2, a2
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mv t3, a3
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addi a4, a4, -1
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2:
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vsetvli t4, t3, e8, m4, ta, ma
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sub t3, t3, t4
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vlseg2e8.v v8, (t0)
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sh1add t0, t4, t0
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vse8.v v8, (t1)
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add t1, t4, t1
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vse8.v v12, (t2)
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add t2, t4, t2
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bnez t3, 2b
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add a0, a0, a5
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add a1, a1, a6
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add a2, a2, a7
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bnez a4, 1b
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ret
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endfunc
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.macro yuy2_to_i422p luma, chroma
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srai t4, a4, 1 // pixel width -> chroma width
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lw t6, (sp)
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slli t5, a4, 1 // pixel width -> (source) byte width
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sub a6, a6, a4
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sub a7, a7, t4
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sub t6, t6, t5
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vsetvli t2, zero, e8, m4, ta, ma
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1:
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mv t4, a4
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addi a5, a5, -1
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2:
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min t0, t2, t4 // ensure even VL on penultimate iteration
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vsetvli t0, t0, e8, m4, ta, ma
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vlseg2e8.v v16, (a3)
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srli t1, t0, 1
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vsetvli zero, t1, e8, m2, ta, ma
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vnsrl.wi v24, \chroma, 0 // U
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sub t4, t4, t0
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vnsrl.wi v28, \chroma, 8 // V
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sh1add a3, t0, a3
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vse8.v v24, (a1)
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add a1, t1, a1
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vse8.v v28, (a2)
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add a2, t1, a2
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vsetvli zero, t0, e8, m4, ta, ma
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vse8.v \luma, (a0)
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add a0, t0, a0
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bnez t4, 2b
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add a3, a3, t6
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add a0, a0, a6
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add a1, a1, a7
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add a2, a2, a7
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bnez a5, 1b
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ret
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.endm
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func ff_uyvytoyuv422_rvv, zve32x
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yuy2_to_i422p v20, v16
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endfunc
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func ff_yuyvtoyuv422_rvv, zve32x
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yuy2_to_i422p v16, v20
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endfunc
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