mirror of
https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
371 lines
10 KiB
NASM
371 lines
10 KiB
NASM
;******************************************************************************
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;* SIMD optimized SAO functions for HEVC 10/12bit decoding
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;*
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;* Copyright (c) 2013 Pierre-Edouard LEPERE
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;* Copyright (c) 2014 James Almer
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA 32
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pw_m2: times 16 dw -2
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pw_mask10: times 16 dw 0x03FF
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pw_mask12: times 16 dw 0x0FFF
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pb_eo: db -1, 0, 1, 0, 0, -1, 0, 1, -1, -1, 1, 1, 1, -1, -1, 1
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cextern pw_m1
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cextern pw_1
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cextern pw_2
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SECTION .text
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;******************************************************************************
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;SAO Band Filter
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;******************************************************************************
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%macro HEVC_SAO_BAND_FILTER_INIT 1
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and leftq, 31
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movd xm0, leftd
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add leftq, 1
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and leftq, 31
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movd xm1, leftd
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add leftq, 1
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and leftq, 31
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movd xm2, leftd
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add leftq, 1
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and leftq, 31
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movd xm3, leftd
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SPLATW m0, xm0
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SPLATW m1, xm1
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SPLATW m2, xm2
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SPLATW m3, xm3
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%if mmsize > 16
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SPLATW m4, [offsetq + 2]
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SPLATW m5, [offsetq + 4]
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SPLATW m6, [offsetq + 6]
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SPLATW m7, [offsetq + 8]
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%else
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movq m7, [offsetq + 2]
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SPLATW m4, m7, 0
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SPLATW m5, m7, 1
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SPLATW m6, m7, 2
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SPLATW m7, m7, 3
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%endif
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%if ARCH_X86_64
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mova m13, [pw_mask %+ %1]
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pxor m14, m14
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%else ; ARCH_X86_32
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mova [rsp+mmsize*0], m0
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mova [rsp+mmsize*1], m1
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mova [rsp+mmsize*2], m2
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mova [rsp+mmsize*3], m3
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mova [rsp+mmsize*4], m4
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mova [rsp+mmsize*5], m5
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mova [rsp+mmsize*6], m6
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mova m1, [pw_mask %+ %1]
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pxor m0, m0
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%define m14 m0
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%define m13 m1
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%define m9 m2
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%define m8 m3
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%endif ; ARCH
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DEFINE_ARGS dst, src, dststride, srcstride, offset, height
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mov heightd, r7m
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%endmacro
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;void ff_hevc_sao_band_filter_<width>_<depth>_<opt>(uint8_t *_dst, const uint8_t *_src, ptrdiff_t _stride_dst, ptrdiff_t _stride_src,
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; int16_t *sao_offset_val, int sao_left_class, int width, int height);
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%macro HEVC_SAO_BAND_FILTER 3
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cglobal hevc_sao_band_filter_%2_%1, 6, 6, 15, 7*mmsize*ARCH_X86_32, dst, src, dststride, srcstride, offset, left
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HEVC_SAO_BAND_FILTER_INIT %1
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align 16
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.loop:
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%assign i 0
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%assign j 0
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%rep %3
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%assign k 8+(j&1)
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%assign l 9-(j&1)
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mova m %+ k, [srcq + i]
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psraw m %+ l, m %+ k, %1-5
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%if ARCH_X86_64
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pcmpeqw m10, m %+ l, m0
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pcmpeqw m11, m %+ l, m1
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pcmpeqw m12, m %+ l, m2
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pcmpeqw m %+ l, m3
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pand m10, m4
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pand m11, m5
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pand m12, m6
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pand m %+ l, m7
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por m10, m11
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por m12, m %+ l
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por m10, m12
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paddw m %+ k, m10
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%else ; ARCH_X86_32
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pcmpeqw m4, m %+ l, [rsp+mmsize*0]
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pcmpeqw m5, m %+ l, [rsp+mmsize*1]
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pcmpeqw m6, m %+ l, [rsp+mmsize*2]
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pcmpeqw m %+ l, [rsp+mmsize*3]
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pand m4, [rsp+mmsize*4]
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pand m5, [rsp+mmsize*5]
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pand m6, [rsp+mmsize*6]
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pand m %+ l, m7
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por m4, m5
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por m6, m %+ l
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por m4, m6
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paddw m %+ k, m4
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%endif ; ARCH
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CLIPW m %+ k, m14, m13
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mova [dstq + i], m %+ k
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%assign i i+mmsize
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%assign j j+1
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%endrep
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add dstq, dststrideq
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add srcq, srcstrideq
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dec heightd
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jg .loop
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RET
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%endmacro
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%macro HEVC_SAO_BAND_FILTER_FUNCS 0
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HEVC_SAO_BAND_FILTER 10, 8, 1
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HEVC_SAO_BAND_FILTER 10, 16, 2
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HEVC_SAO_BAND_FILTER 10, 32, 4
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HEVC_SAO_BAND_FILTER 10, 48, 6
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HEVC_SAO_BAND_FILTER 10, 64, 8
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HEVC_SAO_BAND_FILTER 12, 8, 1
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HEVC_SAO_BAND_FILTER 12, 16, 2
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HEVC_SAO_BAND_FILTER 12, 32, 4
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HEVC_SAO_BAND_FILTER 12, 48, 6
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HEVC_SAO_BAND_FILTER 12, 64, 8
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%endmacro
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INIT_XMM sse2
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HEVC_SAO_BAND_FILTER_FUNCS
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INIT_XMM avx
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HEVC_SAO_BAND_FILTER_FUNCS
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%if HAVE_AVX2_EXTERNAL
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INIT_XMM avx2
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HEVC_SAO_BAND_FILTER 10, 8, 1
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INIT_YMM avx2
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HEVC_SAO_BAND_FILTER 10, 16, 1
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HEVC_SAO_BAND_FILTER 10, 32, 2
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HEVC_SAO_BAND_FILTER 10, 48, 3
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HEVC_SAO_BAND_FILTER 10, 64, 4
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INIT_XMM avx2
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HEVC_SAO_BAND_FILTER 12, 8, 1
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INIT_YMM avx2
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HEVC_SAO_BAND_FILTER 12, 16, 1
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HEVC_SAO_BAND_FILTER 12, 32, 2
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HEVC_SAO_BAND_FILTER 12, 48, 3
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HEVC_SAO_BAND_FILTER 12, 64, 4
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%endif
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;******************************************************************************
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;SAO Edge Filter
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;******************************************************************************
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%define MAX_PB_SIZE 64
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%define PADDING_SIZE 64 ; AV_INPUT_BUFFER_PADDING_SIZE
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%define EDGE_SRCSTRIDE 2 * MAX_PB_SIZE + PADDING_SIZE
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%macro PMINUW 4
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%if cpuflag(sse4)
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pminuw %1, %2, %3
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%else
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psubusw %4, %2, %3
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psubw %1, %2, %4
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%endif
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%endmacro
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%macro HEVC_SAO_EDGE_FILTER_INIT 0
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%if WIN64
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movsxd eoq, dword eom
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%elif ARCH_X86_64
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movsxd eoq, eod
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%else
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mov eoq, r4m
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%endif
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lea tmp2q, [pb_eo]
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movsx a_strideq, byte [tmp2q+eoq*4+1]
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movsx b_strideq, byte [tmp2q+eoq*4+3]
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imul a_strideq, EDGE_SRCSTRIDE >> 1
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imul b_strideq, EDGE_SRCSTRIDE >> 1
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movsx tmpq, byte [tmp2q+eoq*4]
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add a_strideq, tmpq
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movsx tmpq, byte [tmp2q+eoq*4+2]
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add b_strideq, tmpq
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%endmacro
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;void ff_hevc_sao_edge_filter_<width>_<depth>_<opt>(uint8_t *_dst, uint8_t *_src, ptrdiff_t stride_dst, int16_t *sao_offset_val,
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; int eo, int width, int height);
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%macro HEVC_SAO_EDGE_FILTER 3
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%if ARCH_X86_64
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cglobal hevc_sao_edge_filter_%2_%1, 4, 9, 16, dst, src, dststride, offset, eo, a_stride, b_stride, height, tmp
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%define tmp2q heightq
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HEVC_SAO_EDGE_FILTER_INIT
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mov heightd, r6m
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%else ; ARCH_X86_32
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cglobal hevc_sao_edge_filter_%2_%1, 1, 6, 8, 5*mmsize, dst, src, dststride, a_stride, b_stride, height
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%define eoq srcq
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%define tmpq heightq
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%define tmp2q dststrideq
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%define offsetq heightq
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%define m8 m1
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%define m9 m2
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%define m10 m3
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%define m11 m4
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%define m12 m5
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HEVC_SAO_EDGE_FILTER_INIT
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mov srcq, srcm
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mov offsetq, r3m
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mov dststrideq, dststridem
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add a_strideq, a_strideq
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add b_strideq, b_strideq
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%endif ; ARCH
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%if mmsize > 16
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SPLATW m8, [offsetq+2]
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SPLATW m9, [offsetq+4]
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SPLATW m10, [offsetq+0]
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SPLATW m11, [offsetq+6]
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SPLATW m12, [offsetq+8]
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%else
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movq m10, [offsetq+0]
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movd m12, [offsetq+6]
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SPLATW m8, xm10, 1
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SPLATW m9, xm10, 2
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SPLATW m10, xm10, 0
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SPLATW m11, xm12, 0
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SPLATW m12, xm12, 1
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%endif
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pxor m0, m0
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%if ARCH_X86_64
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mova m13, [pw_m1]
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mova m14, [pw_1]
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mova m15, [pw_2]
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%else
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mov heightd, r6m
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mova [rsp+mmsize*0], m8
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mova [rsp+mmsize*1], m9
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mova [rsp+mmsize*2], m10
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mova [rsp+mmsize*3], m11
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mova [rsp+mmsize*4], m12
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%endif
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align 16
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.loop:
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%assign i 0
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%rep %3
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mova m1, [srcq + i]
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movu m2, [srcq+a_strideq + i]
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movu m3, [srcq+b_strideq + i]
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PMINUW m4, m1, m2, m6
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PMINUW m5, m1, m3, m7
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pcmpeqw m2, m4
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pcmpeqw m3, m5
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pcmpeqw m4, m1
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pcmpeqw m5, m1
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psubw m4, m2
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psubw m5, m3
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paddw m4, m5
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pcmpeqw m2, m4, [pw_m2]
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%if ARCH_X86_64
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pcmpeqw m3, m4, m13
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, m14
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pcmpeqw m7, m4, m15
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pand m2, m8
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pand m3, m9
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pand m5, m10
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pand m6, m11
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pand m7, m12
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%else
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pcmpeqw m3, m4, [pw_m1]
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, [pw_1]
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pcmpeqw m7, m4, [pw_2]
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pand m2, [rsp+mmsize*0]
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pand m3, [rsp+mmsize*1]
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pand m5, [rsp+mmsize*2]
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pand m6, [rsp+mmsize*3]
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pand m7, [rsp+mmsize*4]
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%endif
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paddw m2, m3
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paddw m5, m6
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paddw m2, m7
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paddw m2, m1
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paddw m2, m5
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i], m2
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%assign i i+mmsize
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%endrep
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add dstq, dststrideq
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add srcq, EDGE_SRCSTRIDE
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dec heightd
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jg .loop
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RET
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%endmacro
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INIT_XMM sse2
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HEVC_SAO_EDGE_FILTER 10, 8, 1
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HEVC_SAO_EDGE_FILTER 10, 16, 2
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HEVC_SAO_EDGE_FILTER 10, 32, 4
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HEVC_SAO_EDGE_FILTER 10, 48, 6
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HEVC_SAO_EDGE_FILTER 10, 64, 8
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HEVC_SAO_EDGE_FILTER 12, 8, 1
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HEVC_SAO_EDGE_FILTER 12, 16, 2
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HEVC_SAO_EDGE_FILTER 12, 32, 4
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HEVC_SAO_EDGE_FILTER 12, 48, 6
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HEVC_SAO_EDGE_FILTER 12, 64, 8
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%if HAVE_AVX2_EXTERNAL
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INIT_XMM avx2
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HEVC_SAO_EDGE_FILTER 10, 8, 1
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INIT_YMM avx2
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HEVC_SAO_EDGE_FILTER 10, 16, 1
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HEVC_SAO_EDGE_FILTER 10, 32, 2
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HEVC_SAO_EDGE_FILTER 10, 48, 3
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HEVC_SAO_EDGE_FILTER 10, 64, 4
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INIT_XMM avx2
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HEVC_SAO_EDGE_FILTER 12, 8, 1
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INIT_YMM avx2
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HEVC_SAO_EDGE_FILTER 12, 16, 1
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HEVC_SAO_EDGE_FILTER 12, 32, 2
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HEVC_SAO_EDGE_FILTER 12, 48, 3
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HEVC_SAO_EDGE_FILTER 12, 64, 4
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%endif
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