mirror of https://git.ffmpeg.org/ffmpeg.git
301 lines
7.9 KiB
ArmAsm
301 lines
7.9 KiB
ArmAsm
/*
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* Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS).
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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.macro avgdc size
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vwredsumu.vs v16, v8, v16
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vsetivli zero, 1, e16, m1, ta, ma
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vmv.x.s t1, v16
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addi t1, t1, 1 << (\size - 1)
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srai t1, t1, \size
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.endm
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.macro getdc type size
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.ifc \type,top
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vmv.v.x v16, zero
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vle8.v v8, (a3)
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avgdc \size
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.else
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.ifc \type,left
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vmv.v.x v16, zero
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vle8.v v8, (a2)
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avgdc \size
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.else
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.ifc \type,dc
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vmv.v.x v16, zero
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vle8.v v8, (a2)
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vwredsumu.vs v16, v8, v16
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vle8.v v8, (a3)
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avgdc \size
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.else
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li t1, \type
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.endif
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.endif
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.endif
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.endm
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.macro dc_e32 type size n restore
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.ifc \size,32
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li t0, 32
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vsetvli zero, t0, e8, m2, ta, ma
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.else
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vsetivli zero, 16, e8, m1, ta, ma
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.endif
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getdc \type \n
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.if \restore == 1 && \size == 32
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vsetvli zero, t0, e8, m2, ta, ma
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.elseif \restore == 1 && \size == 16
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vsetivli zero, 16, e8, m1, ta, ma
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.endif
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vmv.v.x v0, t1
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.rept \size
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vse8.v v0, (a0)
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add a0, a0, a1
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.endr
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ret
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.endm
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.macro dc_e64 type size n restore
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vsetivli zero, 8, e8, mf2, ta, ma
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getdc \type \n
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li t0, 64
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vsetvli zero, t0, e8, m4, ta, ma
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vmv.v.x v0, t1
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vsetivli zero, 8, e8, mf2, ta, ma
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vsse64.v v0, (a0), a1
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ret
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.endm
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.macro func_dc name size type n restore ext
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func ff_\()\name\()_\()\size\()x\size\()_rvv, \ext
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lpad 0
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.if \size == 8
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dc_e64 \type \size \n \restore
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.else
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dc_e32 \type \size \n \restore
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.endif
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endfunc
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.endm
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func_dc dc_127 32 127 0 0 zve32x
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func_dc dc_127 16 127 0 0 zve32x
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func_dc dc_127 8 127 0 0 zve64x
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func_dc dc_128 32 128 0 0 zve32x
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func_dc dc_128 16 128 0 0 zve32x
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func_dc dc_128 8 128 0 0 zve64x
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func_dc dc_129 32 129 0 0 zve32x
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func_dc dc_129 16 129 0 0 zve32x
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func_dc dc_129 8 129 0 0 zve64x
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func_dc dc 32 dc 6 1 zve32x
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func_dc dc 16 dc 5 1 zve32x
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func_dc dc 8 dc 4 0 zve64x
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func_dc dc_left 32 left 5 1 zve32x
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func_dc dc_left 16 left 4 1 zve32x
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func_dc dc_left 8 left 3 0 zve64x
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func_dc dc_top 32 top 5 1 zve32x
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func_dc dc_top 16 top 4 1 zve32x
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func_dc dc_top 8 top 3 0 zve64x
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func ff_h_32x32_rvv, zve32x
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lpad 0
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li t0, 32
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addi a2, a2, 31
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vsetvli zero, t0, e8, m2, ta, ma
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.rept 2
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.irp n, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
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lbu t1, (a2)
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addi a2, a2, -1
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vmv.v.x v\n, t1
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.endr
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.irp n, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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.endr
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ret
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endfunc
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func ff_h_16x16_rvv, zve32x
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lpad 0
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addi a2, a2, 15
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vsetivli zero, 16, e8, m1, ta, ma
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.irp n, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
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lbu t1, (a2)
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addi a2, a2, -1
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vmv.v.x v\n, t1
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.endr
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.irp n, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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vse8.v v23, (a0)
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ret
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endfunc
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func ff_h_8x8_rvv, zve32x
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lpad 0
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addi a2, a2, 7
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vsetivli zero, 8, e8, mf2, ta, ma
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.irp n, 8, 9, 10, 11, 12, 13, 14, 15
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lbu t1, (a2)
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addi a2, a2, -1
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vmv.v.x v\n, t1
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.endr
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.irp n, 8, 9, 10, 11, 12, 13, 14
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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vse8.v v15, (a0)
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ret
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endfunc
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.macro tm_sum4 dst1, dst2, dst3, dst4, top, n1
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lbu t1, \n1(a2)
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lbu t2, (\n1-1)(a2)
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lbu t3, (\n1-2)(a2)
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lbu t4, (\n1-3)(a2)
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sub t1, t1, a4
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sub t2, t2, a4
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sub t3, t3, a4
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sub t4, t4, a4
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vadd.vx \dst1, \top, t1
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vadd.vx \dst2, \top, t2
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vadd.vx \dst3, \top, t3
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vadd.vx \dst4, \top, t4
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.endm
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func ff_tm_32x32_rvv, zve32x
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lpad 0
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lbu a4, -1(a3)
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li t5, 32
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.irp offset, 31, 23, 15, 7
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vsetvli zero, t5, e16, m4, ta, ma
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vle8.v v8, (a3)
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vzext.vf2 v28, v8
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tm_sum4 v0, v4, v8, v12, v28, \offset
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tm_sum4 v16, v20, v24, v28, v28, (\offset-4)
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.irp n, 0, 4, 8, 12, 16, 20, 24, 28
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, m2, ta, ma
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.irp n, 0, 4, 8, 12, 16, 20, 24, 28
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vnclipu.wi v\n, v\n, 0
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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.endr
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ret
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endfunc
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func ff_tm_16x16_rvv, zve32x
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vsetivli zero, 16, e16, m2, ta, ma
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vle8.v v8, (a3)
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vzext.vf2 v30, v8
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lbu a4, -1(a3)
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tm_sum4 v0, v2, v4, v6, v30, 15
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tm_sum4 v8, v10, v12, v14, v30, 11
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tm_sum4 v16, v18, v20, v22, v30, 7
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tm_sum4 v24, v26, v28, v30, v30, 3
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.irp n, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, m1, ta, ma
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.irp n, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28
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vnclipu.wi v\n, v\n, 0
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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vnclipu.wi v30, v30, 0
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vse8.v v30, (a0)
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ret
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endfunc
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func ff_tm_8x8_rvv, zve32x
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lpad 0
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vsetivli zero, 8, e16, m1, ta, ma
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vle8.v v8, (a3)
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vzext.vf2 v28, v8
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lbu a4, -1(a3)
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tm_sum4 v16, v17, v18, v19, v28, 7
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tm_sum4 v20, v21, v22, v23, v28, 3
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.irp n, 16, 17, 18, 19, 20, 21, 22, 23
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, mf2, ta, ma
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.irp n, 16, 17, 18, 19, 20, 21, 22
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vnclipu.wi v\n, v\n, 0
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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vnclipu.wi v24, v23, 0
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vse8.v v24, (a0)
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ret
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endfunc
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func ff_tm_4x4_rvv, zve32x
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lpad 0
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vsetivli zero, 4, e16, mf2, ta, ma
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vle8.v v8, (a3)
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vzext.vf2 v28, v8
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lbu a4, -1(a3)
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tm_sum4 v16, v17, v18, v19, v28, 3
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.irp n, 16, 17, 18, 19
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, mf4, ta, ma
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.irp n, 16, 17, 18
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vnclipu.wi v\n, v\n, 0
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vse8.v v\n, (a0)
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add a0, a0, a1
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.endr
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vnclipu.wi v24, v19, 0
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vse8.v v24, (a0)
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ret
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endfunc
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