Commit Graph

116609 Commits

Author SHA1 Message Date
James Almer
09de979ff6 avcodec/amfenc_av1: use AV_WL32A
Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-29 21:33:31 -03:00
James Almer
753f2aeed7 avutil/intreadwrite: add missing aligned read/write macros
Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-29 21:33:31 -03:00
Rémi Denis-Courmont
7b24f96c87 lavc/vp9dsp: remove R-V I intra functions
At this point, they are identical to the C code, except for instruction
ordering. In fact, they are typically slower or no faster than the C code.
2024-07-29 21:16:41 +03:00
Rémi Denis-Courmont
7aa6510fe1 lavc/vp9dsp: copy 8 pixels at once
In the 8-bit case, we can actually read/write 8 aligned pixel values per
load/store, which unsurprisingly tends to be faster on 64-bit systems (and
makes no differences on 32-bit systems). This requires ifdef'ing though.
2024-07-29 21:16:41 +03:00
Rémi Denis-Courmont
c98127c00e lavc/vp9dsp: use restrict qualifier for copy/avg MC
Same as previous commit.
2024-07-29 21:16:41 +03:00
Rémi Denis-Courmont
56fc5fc6ce lavc/vp9dsp: restrict vertical intra pointers
This lets the compiler unroll ever so slightly better (at least in the
16x16 case for RISC-V GCC).
2024-07-29 21:16:41 +03:00
James Almer
afb06aef7e avcodec/decode: remove unused argument from ff_frame_new_side_data_from_buf()
Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-29 14:00:48 -03:00
James Almer
e7d3ff8dcd avformat/mov: check that child boxes of trak are only present inside it
Based on the check done for the stco box.

Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-28 17:28:19 -03:00
James Almer
2aa63784b5 avformat/mov: check that sample and chunk count is 1 for HEIF
Fixes NULL pointer dereference in broken/fuzzed streams.

Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-28 17:28:19 -03:00
Rémi Denis-Courmont
39ced529b0 lavu/riscv: implement floating point clips
Unlike x86, fmin/fmax are single instructions, not function calls. They
are much much faster than doing a comparison, then branching based on its
results. With this, audiodsp.vector_clipf gets almost twice as fast, and
a properly unrollled version of it gets 4-5x faster, on SiFive-U74.
This is only the low-hanging fruit: FFMIN and FFMAX are presumably
affected as well.

This likely applies to other instruction sets with native IEEE floats,
especially those lacking a conditional select instruction.
2024-07-28 21:24:58 +03:00
Rémi Denis-Courmont
b0b3bea10b lavc/h264dsp: use saturing add/sub for R-V V 8-bit DC add
T-Head C908 (cycles):
h264_idct4_dc_add_8bpp_c:      109.2
h264_idct4_dc_add_8bpp_rvv_i32: 34.5 (before)
h264_idct4_dc_add_8bpp_rvv_i32: 25.5 (after)
h264_idct8_dc_add_8bpp_c:      418.7
h264_idct8_dc_add_8bpp_rvv_i64: 69.5 (before)
h264_idct8_dc_add_8bpp_rvv_i64: 33.5 (after)
2024-07-28 21:24:12 +03:00
Shiyou Yin
4713a5cc24
swscale: [loongarch] Fix checkasm-sw_yuv2rgb failure.
Reviewed-by: 陈昊 <chenhao@loongson.cn>
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2024-07-28 19:02:16 +02:00
Michael Niedermayer
3b9c6c7fbb
avcodec/adpcm: Remove setting min_channel to value it is already set to
Reviewed-by: Peter Ross <pross@xvid.org>
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2024-07-28 19:02:15 +02:00
Tong Wu
b1d410716b lavc/d3d12va_encode: trim header alignment at output
It is d3d12va's requirement that the FrameStartOffset must be aligned as
per hardware limitation. However, we could trim this alignment at output
to reduce coded size. A aligned_header_size is added to
D3D12VAEncodePicture.

Signed-off-by: Tong Wu <wutong1208@outlook.com>
2024-07-28 17:50:30 +02:00
Rémi Denis-Courmont
9b4655c3a1 lavc/vp8dsp: use saturating add/sub for R-V V DC add
T-Head C908 (cycles):
vp7_idct_dc_add_c:          108.5
vp7_idct_dc_add_rvv_i32:     56.2 (before)
vp7_idct_dc_add_rvv_i32:     47.2 (after)
vp8_idct_dc_add_c:           96.2
vp8_idct_dc_add_rvv_i32:     43.0 (before)
vp8_idct_dc_add_rvv_i32:     34.0 (after)
2024-07-28 17:37:21 +03:00
Rémi Denis-Courmont
bbfc0ac9ca lavc/riscv: don't set vxrm if unnecessary
While narrowing clip is nominally a rounding operation, the rounding mode
has no arithmetic consequence if the right shift is by zero bits.
2024-07-28 17:37:21 +03:00
Niklas Haas
e42a0763b7 avcodec/dovi_rpudec: clarify semantics
ff_dovi_rpu_parse() and ff_dovi_rpu_generate() are a bit inconsistent in
that they expect different levels of encapsulation, due to the nature of
how this is handled in the context of different APIs. Clarify the status
quo. (And fix an incorrect reference to the RPU payload bytes as 'RBSP')
2024-07-28 12:20:07 +02:00
Niklas Haas
6b66df74b8 avcodec/dovi_rpu: correctly copy num_ext_blocks 2024-07-28 12:20:07 +02:00
Niklas Haas
b5aeafc00a fftools/ffprobe: implement dv_md_compression 2024-07-28 12:20:07 +02:00
Niklas Haas
3d5d60d041 avformat/dump: implement dv_md_compression 2024-07-28 12:20:07 +02:00
Niklas Haas
ce8166a19c avformat/mpegts: implement dv_md_compression 2024-07-28 12:20:07 +02:00
Niklas Haas
b3a9fab9da avformat/dovi_isom: implement dv_md_compression 2024-07-28 12:20:07 +02:00
Niklas Haas
cbea92c84d avutil/dovi_meta: add dv_md_compression to cfg record
This field is used to signal the compression method in use.
2024-07-28 12:20:07 +02:00
Zhao Zhili
719e46f54c avcodec/videotoolboxenc: Fix variable type of AV_OPT_TYPE_BOOL
Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
2024-07-26 19:54:56 +08:00
Zhao Zhili
f4e0f40230 avcodec/videotoolboxenc: Set default bitrate to zero
Zero is auto mode. From the doc of videotoolbox:

   The default bit rate is zero, which indicates that the video
   encoder should determine the size of compressed data.

Before the patch, the default bitrate is 200000 setting by
avcodec/options_table, which doesn't work for most of cases.

Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
2024-07-26 19:54:20 +08:00
Zhao Zhili
d07da7539d avcodec/videotoolboxenc: Fix bitrate doesn't work as expected
Commit 4ef5e7d472 add qmin/qmax support to videotoolbox encoder.
The default value of (qmin, qmax) is (2, 31), which makes bitrate
control doesn't work as users' expectations.

Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
2024-07-26 19:54:20 +08:00
Rémi Denis-Courmont
8030876d1c checkasm/riscv: align the landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
7dde8be29f checkasm/riscv: add forward-edge CFI landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
4f2472909e sws/riscv: add forward-edge CFI landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
b5c111272b lavfi/riscv: add forward-edge CFI landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
f2c30fe15a lavc/riscv: add forward-edge CFI landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
a14d21a446 lavu/riscv: add forward-edge CFI landing pads 2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
6319601343 lavu/riscv: assembly for zicfilp LPAD
This instruction, if aligned on a 4-byte boundary, defines a valid target
("landing pad") for an indirect call or jump. Since this instruction is a
HINT, it is safe to assemble even if not included in the target
instruction set architecture.

The necessary alignment is already provided by the `func` macro. However
this still lacks the ELF attribute to indicate that the zicfilp is supported
in simple mode. This is left for future work as the ELF specification is not
ratified as of yet.

This will also nonobviously require the assembler to support zicfilp,
insofar as the `tail` pseudo-instruction shall clobber T2 (instead of T1) as
its temporary register.
2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
982376660c lavu/riscv: align functions to 4 bytes
Currently the start of the byte range for each function is aligned to
4 bytes. But this can lead to situations whence the function is preceded
by a 2-byte C.NOP at the aligned 4-byte boundary. Then the first actual
instruction and the function symbol are only aligned on 2 bytes.

This forcefully disables compression for the alignment and the symbol,
thus ensuring that there is no padding before the function.
2024-07-25 23:10:14 +03:00
Rémi Denis-Courmont
b62586e310 lavc/h264dsp: use RISC-V B extension
This saves one register and one instruction per transform.
add16 and add16intra thus become stack-less.
2024-07-25 23:10:01 +03:00
Rémi Denis-Courmont
45d7078a21 lavu/riscv: add CPU flag for B bit manipulations
The B extension was finally ratified in May 2024, encompassing:
- Zba (addresses),
- Zbb (basics) and
- Zbs (single bits).
It does not include Zbc (base-2 polynomials).
2024-07-25 23:09:58 +03:00
Rémi Denis-Courmont
529d423012 lavu/riscv: remove bespoke SH{1,2,3}ADD assembler
configure checks that the assembler supports the B extension (or rather
its constituents) anyway. These macros were dodging sanity checks for
unsupported instructions and nothing else.
2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
5f10173fa1 lavu/riscv: require B or zba explicitly 2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
e91a8cc4de sws/riscv: require B or zba explicitly 2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
9108f3e5e1 lavfi/riscv: require B or zba explicitly 2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
187d4d066a lavc/riscv: require B or zba explicitly 2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
7f97344bfb lavu/riscv: grok B as an extension
The RISC-V B bit manipulation extension was ratified only two months ago.
But it is strictly equivalent to the union of the zba, zbb and zbs
extensions which were defined almost 3 years earlier. Rather than require
new assembler, we can just match the extension name manually and translate
it into its constituent parts.
2024-07-25 18:55:48 +03:00
Rémi Denis-Courmont
1e7ab200ee lavu/riscv: allow any number of extensions
This reworks the func/endfunc macros to support any number of ISA extension
as parameters.
2024-07-25 18:55:48 +03:00
Araz Iusubov
2128c17739 avcodec/amf_enc: av1 cropping support
Signed-off-by: James Almer <jamrial@gmail.com>
2024-07-25 10:22:02 -03:00
Rémi Denis-Courmont
896c22ef00 lavc/vp8dsp: fix RV32 stack alignment
SP must be a multiple of 16 bytes at all times on POSIX - even in leaf
functions - so that signal handlers have a properly aligned stack.
2024-07-24 22:08:54 +03:00
Jens Frederich
60b1750134
avdevice/dshow: Don't skip audio devices if no video device is present
The search of the current DirectShow device list has been customized so
that audio devices are always found even if no video device is connected.

Signed-off-by: Jens Frederich <jens.frederich@vector.com>
Reviewed-by: Roger Pack <rogerdpack2@gmail.com>
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2024-07-24 14:45:20 +02:00
Martin Storsjö
97a708a507 checkasm: Increase the tolerance for ac3_sum_square_butterfly_float
Increase the tolerance from 10 ulp to 11 ulp. This fixes occasional
errors for some inputs; the errors could be reproduced on
aarch64/neon builds, with "checkasm --test=ac3dsp 3446175925".

Signed-off-by: Martin Storsjö <martin@martin.st>
2024-07-24 12:10:33 +03:00
Anton Khirnov
d1fa39d08d fftools/ffmpeg: prefer real errors over EOF in err_merge()
Fixes an issue in 6.1 when reading a corrupted file with -xerror would
exit with success. This specific issue is not present in master, but
this should generally be a more robust behaviour.

Reported-by: Andrej Peterka
2024-07-24 08:20:21 +02:00
Lynne
b1b69ccbc0
aacdec: set ac->output_elements upon channel element free
The issue is that ac->output_elements is populated from
ac->che, which may be freed, leaving dangling pointers in this
list.

Should fix clusterfuzz.
2024-07-24 00:32:38 +02:00
Michael Niedermayer
204f7f8cc7
avcodec/hdrenc: Allocate more space
This needs to be double checked or a checking way of writing should be used

Fixes: out of array access
Fixes: 70007/clusterfuzz-testcase-minimized-ffmpeg_AV_CODEC_ID_HDR_fuzzer-5478704150020096

Found-by: continuous fuzzing process https://github.com/google/oss-fuzz/tree/master/projects/ffmpeg
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2024-07-23 23:21:17 +02:00