mirror of https://git.ffmpeg.org/ffmpeg.git
x86: hevc_mc: specify coefficients registers
By default, macro EPEL_FILTER loads the coefficients inconditionally into m14/m15. This forces an unneeded higher register count. Reduce that count by making them parameters of EPEL_FILTER. Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Christophe Gisquet
Michael Niedermayer
parent
0a15067047
commit
f1793fe9cd
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@ -112,7 +112,7 @@ QPEL_TABLE 10, 4, w, sse4
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%endif
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%endmacro
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%macro EPEL_FILTER 2 ; bit depth, filter index
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%macro EPEL_FILTER 2-4 ; bit depth, filter index
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%ifdef PIC
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lea rfilterq, [hevc_epel_filters_sse4_%1]
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%else
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@ -120,8 +120,13 @@ QPEL_TABLE 10, 4, w, sse4
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%endif
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sub %2q, 1
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shl %2q, 5 ; multiply by 32
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%if %0 == 2
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movdqa m14, [rfilterq + %2q] ; get 2 first values of filters
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movdqa m15, [rfilterq + %2q+16] ; get 2 last values of filters
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%else
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movdqa %3, [rfilterq + %2q] ; get 2 first values of filters
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movdqa %4, [rfilterq + %2q+16] ; get 2 last values of filters
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%endif
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%endmacro
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%macro EPEL_HV_FILTER 1
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@ -539,24 +544,24 @@ cglobal hevc_put_hevc_bi_pel_pixels%1_%2, 7, 7, 6, dst, dststride, src, srcstrid
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%macro HEVC_PUT_HEVC_EPEL 2
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cglobal hevc_put_hevc_epel_h%1_%2, 6, 7, 15 , dst, dststride, src, srcstride, height, mx, rfilter
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cglobal hevc_put_hevc_epel_h%1_%2, 6, 7, 6, dst, dststride, src, srcstride, height, mx, rfilter
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%assign %%stride ((%2 + 7)/8)
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EPEL_FILTER %2, mx
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EPEL_FILTER %2, mx, m4, m5
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.loop
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EPEL_LOAD %2, srcq-%%stride, %%stride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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EPEL_COMPUTE %2, %1, m4, m5
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PEL_10STORE%1 dstq, m0, m1
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LOOP_END dst, dststride, src, srcstride
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RET
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cglobal hevc_put_hevc_uni_epel_h%1_%2, 6, 7, 15 , dst, dststride, src, srcstride, height, mx, rfilter
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cglobal hevc_put_hevc_uni_epel_h%1_%2, 6, 7, 7, dst, dststride, src, srcstride, height, mx, rfilter
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%assign %%stride ((%2 + 7)/8)
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movdqa m9, [pw_%2]
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EPEL_FILTER %2, mx
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movdqa m6, [pw_%2]
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EPEL_FILTER %2, mx, m4, m5
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.loop
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EPEL_LOAD %2, srcq-%%stride, %%stride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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UNI_COMPUTE %1, %2, m0, m1, m9
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EPEL_COMPUTE %2, %1, m4, m5
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UNI_COMPUTE %1, %2, m0, m1, m6
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PEL_%2STORE%1 dstq, m0, m1
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lea dstq, [dstq+dststrideq] ; dst += dststride
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lea srcq, [srcq+srcstrideq] ; src += srcstride
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@ -564,14 +569,14 @@ cglobal hevc_put_hevc_uni_epel_h%1_%2, 6, 7, 15 , dst, dststride, src, srcstride
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jnz .loop ; height loop
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RET
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cglobal hevc_put_hevc_bi_epel_h%1_%2, 8, 9, 15, dst, dststride, src, srcstride, src2, src2stride,height, mx, rfilter
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movdqa m9, [pw_bi_%2]
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EPEL_FILTER %2, mx
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cglobal hevc_put_hevc_bi_epel_h%1_%2, 8, 9, 7, dst, dststride, src, srcstride, src2, src2stride,height, mx, rfilter
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movdqa m6, [pw_bi_%2]
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EPEL_FILTER %2, mx, m4, m5
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.loop
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EPEL_LOAD %2, srcq-%%stride, %%stride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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EPEL_COMPUTE %2, %1, m4, m5
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SIMPLE_BILOAD %1, src2q, m2, m3
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BI_COMPUTE %1, %2, m0, m1, m2, m3, m9
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BI_COMPUTE %1, %2, m0, m1, m2, m3, m6
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PEL_%2STORE%1 dstq, m0, m1
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lea dstq, [dstq+dststrideq] ; dst += dststride
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lea srcq, [srcq+srcstrideq] ; src += srcstride
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@ -587,26 +592,26 @@ cglobal hevc_put_hevc_bi_epel_h%1_%2, 8, 9, 15, dst, dststride, src, srcstride,
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; int16_t* mcbuffer)
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; ******************************
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cglobal hevc_put_hevc_epel_v%1_%2, 7, 8, 15 , dst, dststride, src, srcstride, height, r3src, my, rfilter
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cglobal hevc_put_hevc_epel_v%1_%2, 7, 8, 6, dst, dststride, src, srcstride, height, r3src, my, rfilter
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lea r3srcq, [srcstrideq*3]
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sub srcq, srcstrideq
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EPEL_FILTER %2, my
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EPEL_FILTER %2, my, m4, m5
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.loop
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EPEL_LOAD %2, srcq, srcstride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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EPEL_COMPUTE %2, %1, m4, m5
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PEL_10STORE%1 dstq, m0, m1
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LOOP_END dst, dststride, src, srcstride
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RET
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cglobal hevc_put_hevc_uni_epel_v%1_%2, 7, 8, 15 , dst, dststride, src, srcstride, height, r3src, my, rfilter
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cglobal hevc_put_hevc_uni_epel_v%1_%2, 7, 8, 7, dst, dststride, src, srcstride, height, r3src, my, rfilter
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lea r3srcq, [srcstrideq*3]
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movdqa m9, [pw_%2]
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movdqa m6, [pw_%2]
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sub srcq, srcstrideq
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EPEL_FILTER %2, my
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EPEL_FILTER %2, my, m4, m5
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.loop
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EPEL_LOAD %2, srcq, srcstride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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UNI_COMPUTE %1, %2, m0, m1, m9
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EPEL_COMPUTE %2, %1, m4, m5
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UNI_COMPUTE %1, %2, m0, m1, m6
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PEL_%2STORE%1 dstq, m0, m1
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lea dstq, [dstq+dststrideq] ; dst += dststride
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lea srcq, [srcq+srcstrideq] ; src += srcstride
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@ -615,16 +620,16 @@ cglobal hevc_put_hevc_uni_epel_v%1_%2, 7, 8, 15 , dst, dststride, src, srcstride
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RET
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cglobal hevc_put_hevc_bi_epel_v%1_%2, 9, 10, 15, dst, dststride, src, srcstride, src2, src2stride,height, r3src, my, rfilter
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cglobal hevc_put_hevc_bi_epel_v%1_%2, 9, 10, 7, dst, dststride, src, srcstride, src2, src2stride,height, r3src, my, rfilter
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lea r3srcq, [srcstrideq*3]
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movdqa m9, [pw_bi_%2]
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movdqa m6, [pw_bi_%2]
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sub srcq, srcstrideq
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EPEL_FILTER %2, my
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EPEL_FILTER %2, my, m4, m5
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.loop
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EPEL_LOAD %2, srcq, srcstride, %1
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EPEL_COMPUTE %2, %1, m14, m15
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EPEL_COMPUTE %2, %1, m4, m5
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SIMPLE_BILOAD %1, src2q, m2, m3
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BI_COMPUTE %1, %2, m0, m1, m2, m3, m9
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BI_COMPUTE %1, %2, m0, m1, m2, m3, m6
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PEL_%2STORE%1 dstq, m0, m1
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lea dstq, [dstq+dststrideq] ; dst += dststride
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lea srcq, [srcq+srcstrideq] ; src += srcstride
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