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lavc/aacpsdsp: rework R-V V add_squares
Segmented loads may be slower than not. So this advantageously uses a unit-strided load and narrowing shifts instead. Before: ps_add_squares_c: 60757.7 ps_add_squares_rvv_f32: 22242.5 After: ps_add_squares_c: 60516.0 ps_add_squares_rvv_i64: 17067.7
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@ -46,7 +46,8 @@ av_cold void ff_psdsp_init_riscv(PSDSPContext *c)
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c->hybrid_analysis = ff_ps_hybrid_analysis_rvv;
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if (flags & AV_CPU_FLAG_RVB_ADDR) {
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c->add_squares = ff_ps_add_squares_rvv;
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if (flags & AV_CPU_FLAG_RVV_I64)
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c->add_squares = ff_ps_add_squares_rvv;
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c->mul_pair_single = ff_ps_mul_pair_single_rvv;
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c->stereo_interpolate[0] = ff_ps_stereo_interpolate_rvv;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright © 2022 Rémi Denis-Courmont.
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* Copyright © 2022-2023 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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@ -20,13 +20,16 @@
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#include "libavutil/riscv/asm.S"
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func ff_ps_add_squares_rvv, zve32f
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func ff_ps_add_squares_rvv, zve64f
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li t1, 32
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1:
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vsetvli t0, a2, e32, m4, ta, ma
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vlseg2e32.v v24, (a1)
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vle64.v v8, (a1)
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sub a2, a2, t0
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vnsrl.wx v24, v8, zero
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vle32.v v16, (a0)
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sh3add a1, t0, a1
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vnsrl.wx v28, v8, t1
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vfmacc.vv v16, v24, v24
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vfmacc.vv v16, v28, v28
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vse32.v v16, (a0)
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