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swscale/x86/input: add AVX2 optimized RGB24 to YUV functions
rgb24_to_uv_8_c: 39.3 rgb24_to_uv_8_sse2: 14.3 rgb24_to_uv_8_ssse3: 13.3 rgb24_to_uv_8_avx: 12.8 rgb24_to_uv_8_avx2: 14.3 rgb24_to_uv_128_c: 582.8 rgb24_to_uv_128_sse2: 127.3 rgb24_to_uv_128_ssse3: 107.3 rgb24_to_uv_128_avx: 111.3 rgb24_to_uv_128_avx2: 62.3 rgb24_to_uv_1080_c: 4981.3 rgb24_to_uv_1080_sse2: 1048.3 rgb24_to_uv_1080_ssse3: 876.8 rgb24_to_uv_1080_avx: 887.8 rgb24_to_uv_1080_avx2: 492.3 rgb24_to_uv_1280_c: 5906.8 rgb24_to_uv_1280_sse2: 1263.3 rgb24_to_uv_1280_ssse3: 1048.3 rgb24_to_uv_1280_avx: 1045.8 rgb24_to_uv_1280_avx2: 579.8 rgb24_to_uv_1920_c: 8665.3 rgb24_to_uv_1920_sse2: 1888.8 rgb24_to_uv_1920_ssse3: 1571.8 rgb24_to_uv_1920_avx: 1558.8 rgb24_to_uv_1920_avx2: 869.3 rgb24_to_y_8_c: 20.3 rgb24_to_y_8_sse2: 11.8 rgb24_to_y_8_ssse3: 10.3 rgb24_to_y_8_avx: 10.3 rgb24_to_y_8_avx2: 10.8 rgb24_to_y_128_c: 284.8 rgb24_to_y_128_sse2: 83.3 rgb24_to_y_128_ssse3: 66.8 rgb24_to_y_128_avx: 64.8 rgb24_to_y_128_avx2: 39.3 rgb24_to_y_1080_c: 2451.3 rgb24_to_y_1080_sse2: 696.3 rgb24_to_y_1080_ssse3: 516.8 rgb24_to_y_1080_avx: 518.8 rgb24_to_y_1080_avx2: 301.8 rgb24_to_y_1280_c: 2892.8 rgb24_to_y_1280_sse2: 816.8 rgb24_to_y_1280_ssse3: 623.3 rgb24_to_y_1280_avx: 616.3 rgb24_to_y_1280_avx2: 350.8 rgb24_to_y_1920_c: 4338.8 rgb24_to_y_1920_sse2: 1210.8 rgb24_to_y_1920_ssse3: 928.3 rgb24_to_y_1920_avx: 920.3 rgb24_to_y_1920_avx2: 534.8 Signed-off-by: James Almer <jamrial@gmail.com>
This commit is contained in:
James Almer
parent
6743c2fc6a
commit
d5fe99dc5f
@ -23,7 +23,7 @@
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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SECTION_RODATA 32
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%define RY 0x20DE
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%define GY 0x4087
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@ -90,8 +90,12 @@ rgb_UVrnd: times 4 dd 0x400100 ; 128.5 << 15
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; rgba_Vcoeff_ag: times 4 dw 0, GV
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shuf_rgb_12x4: db 0, 0x80, 1, 0x80, 2, 0x80, 3, 0x80, \
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6, 0x80, 7, 0x80, 8, 0x80, 9, 0x80, \
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0, 0x80, 1, 0x80, 2, 0x80, 3, 0x80, \
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6, 0x80, 7, 0x80, 8, 0x80, 9, 0x80
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shuf_rgb_3x56: db 2, 0x80, 3, 0x80, 4, 0x80, 5, 0x80, \
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8, 0x80, 9, 0x80, 10, 0x80, 11, 0x80, \
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2, 0x80, 3, 0x80, 4, 0x80, 5, 0x80, \
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8, 0x80, 9, 0x80, 10, 0x80, 11, 0x80
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pd_65535f: times 8 dd 65535.0
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pb_pack_shuffle16le: db 0, 1, 4, 5, \
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@ -134,8 +138,13 @@ SECTION .text
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%macro RGB24_TO_Y_FN 2-3
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cglobal %2 %+ 24ToY, 6, 6, %1, dst, src, u1, u2, w, table
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%if ARCH_X86_64
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%if mmsize == 32
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vbroadcasti128 m8, [%2_Ycoeff_12x4]
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vbroadcasti128 m9, [%2_Ycoeff_3x56]
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%else
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mova m8, [%2_Ycoeff_12x4]
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mova m9, [%2_Ycoeff_3x56]
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%endif
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%define coeff1 m8
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%define coeff2 m9
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%else ; x86-32
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@ -165,11 +174,19 @@ cglobal %2 %+ 24ToY, 6, 6, %1, dst, src, u1, u2, w, table
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%if notcpuflag(ssse3)
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pxor m7, m7
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%endif ; !cpuflag(ssse3)
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%if mmsize == 32
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vbroadcasti128 m4, [rgb_Yrnd]
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%else
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mova m4, [rgb_Yrnd]
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%endif
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.loop:
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%if cpuflag(ssse3)
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movu m0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
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movu m2, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
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movu xm0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
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movu xm2, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
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%if mmsize == 32
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vinserti128 m0, m0, [srcq+24], 1
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vinserti128 m2, m2, [srcq+36], 1
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%endif
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pshufb m1, m0, shuf_rgb2 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
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pshufb m0, shuf_rgb1 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
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pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
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@ -212,27 +229,35 @@ cglobal %2 %+ 24ToY, 6, 6, %1, dst, src, u1, u2, w, table
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%endmacro
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; %1 = nr. of XMM registers
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; %2 = rgb or bgr
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%macro RGB24_TO_UV_FN 2-3
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cglobal %2 %+ 24ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
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; %2 = aligned/unaligned output argument
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; %3-4 = rgb or bgr
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%macro RGB24_TO_UV_FN 3-4
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cglobal %3 %+ 24ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
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%if ARCH_X86_64
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mova m8, [%2_Ucoeff_12x4]
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mova m9, [%2_Ucoeff_3x56]
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mova m10, [%2_Vcoeff_12x4]
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mova m11, [%2_Vcoeff_3x56]
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%if mmsize == 32
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vbroadcasti128 m8, [%3_Ucoeff_12x4]
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vbroadcasti128 m9, [%3_Ucoeff_3x56]
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vbroadcasti128 m10, [%3_Vcoeff_12x4]
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vbroadcasti128 m11, [%3_Vcoeff_3x56]
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%else
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mova m8, [%3_Ucoeff_12x4]
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mova m9, [%3_Ucoeff_3x56]
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mova m10, [%3_Vcoeff_12x4]
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mova m11, [%3_Vcoeff_3x56]
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%endif
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%define coeffU1 m8
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%define coeffU2 m9
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%define coeffV1 m10
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%define coeffV2 m11
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%else ; x86-32
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%define coeffU1 [%2_Ucoeff_12x4]
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%define coeffU2 [%2_Ucoeff_3x56]
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%define coeffV1 [%2_Vcoeff_12x4]
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%define coeffV2 [%2_Vcoeff_3x56]
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%define coeffU1 [%3_Ucoeff_12x4]
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%define coeffU2 [%3_Ucoeff_3x56]
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%define coeffV1 [%3_Vcoeff_12x4]
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%define coeffV2 [%3_Vcoeff_3x56]
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%endif ; x86-32/64
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%if ARCH_X86_64 && %0 == 3
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jmp mangle(private_prefix %+ _ %+ %3 %+ 24ToUV %+ SUFFIX).body
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%else ; ARCH_X86_64 && %0 == 3
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%if ARCH_X86_64 && %0 == 4
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jmp mangle(private_prefix %+ _ %+ %4 %+ 24ToUV %+ SUFFIX).body
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%else ; ARCH_X86_64 && %0 == 4
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.body:
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%if cpuflag(ssse3)
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mova m7, [shuf_rgb_12x4]
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@ -253,14 +278,22 @@ cglobal %2 %+ 24ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
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add dstUq, wq
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add dstVq, wq
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neg wq
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%if mmsize == 32
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vbroadcasti128 m6, [rgb_UVrnd]
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%else
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mova m6, [rgb_UVrnd]
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%endif
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%if notcpuflag(ssse3)
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pxor m7, m7
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%endif
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.loop:
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%if cpuflag(ssse3)
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movu m0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
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movu m4, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
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movu xm0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
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movu xm4, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
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%if mmsize == 32
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vinserti128 m0, m0, [srcq+24], 1
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vinserti128 m4, m4, [srcq+36], 1
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%endif
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pshufb m1, m0, shuf_rgb2 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
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pshufb m0, shuf_rgb1 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
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%else ; !cpuflag(ssse3)
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@ -309,32 +342,40 @@ cglobal %2 %+ 24ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
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psrad m4, 9
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packssdw m0, m1 ; (word) { U[0-7] }
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packssdw m2, m4 ; (word) { V[0-7] }
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mova [dstUq+wq], m0
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mova [dstVq+wq], m2
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mov%2 [dstUq+wq], m0
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mov%2 [dstVq+wq], m2
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add wq, mmsize
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jl .loop
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RET
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%endif ; ARCH_X86_64 && %0 == 3
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%endif ; ARCH_X86_64 && %0 == 4
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%endmacro
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; %1 = nr. of XMM registers for rgb-to-Y func
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; %2 = nr. of XMM registers for rgb-to-UV func
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%macro RGB24_FUNCS 2
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; %3 = aligned/unaligned output argument
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%macro RGB24_FUNCS 3
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RGB24_TO_Y_FN %1, rgb
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RGB24_TO_Y_FN %1, bgr, rgb
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RGB24_TO_UV_FN %2, rgb
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RGB24_TO_UV_FN %2, bgr, rgb
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RGB24_TO_UV_FN %2, %3, rgb
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RGB24_TO_UV_FN %2, %3, bgr, rgb
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%endmacro
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INIT_XMM sse2
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RGB24_FUNCS 10, 12
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RGB24_FUNCS 10, 12, a
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INIT_XMM ssse3
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RGB24_FUNCS 11, 13
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RGB24_FUNCS 11, 13, a
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%if HAVE_AVX_EXTERNAL
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INIT_XMM avx
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RGB24_FUNCS 11, 13
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RGB24_FUNCS 11, 13, a
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%endif
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%if ARCH_X86_64
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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RGB24_FUNCS 11, 13, u
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%endif
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%endif
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; %1 = nr. of XMM registers
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@ -321,6 +321,8 @@ void ff_ ## fmt ## ToUV_ ## opt(uint8_t *dstU, uint8_t *dstV, \
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INPUT_FUNCS(sse2);
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INPUT_FUNCS(ssse3);
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INPUT_FUNCS(avx);
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INPUT_FUNC(rgb24, avx2);
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INPUT_FUNC(bgr24, avx2);
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#if ARCH_X86_64
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#define YUV2NV_DECL(fmt, opt) \
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@ -634,6 +636,11 @@ switch(c->dstBpc){ \
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}
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if (EXTERNAL_AVX2_FAST(cpu_flags)) {
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if (ARCH_X86_64)
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switch (c->srcFormat) {
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case_rgb(rgb24, RGB24, avx2);
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case_rgb(bgr24, BGR24, avx2);
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}
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switch (c->dstFormat) {
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case AV_PIX_FMT_NV12:
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case AV_PIX_FMT_NV24:
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