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vp9: fix msvc build by using 6 GPRs on 32bit if stack!=aligned.
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@ -1634,8 +1634,13 @@ cglobal vp9_ipred_hu_16x16_16, 3, 4, 6 + notcpuflag(ssse3), dst, stride, l, a
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jg .loop
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RET
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%if ARCH_X86_64 || HAVE_ALIGNED_STACK
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cglobal vp9_ipred_hu_32x32_16, 3, 7, 10 + notcpuflag(ssse3), \
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%1 * mmsize * ARCH_X86_32, dst, stride, l, a
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%else
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cglobal vp9_ipred_hu_32x32_16, 3, 6, 10 + notcpuflag(ssse3), \
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%1 * mmsize * ARCH_X86_32, dst, stride, l, a
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%endif
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mova m2, [lq+mmsize*0+0]
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movu m1, [lq+mmsize*0+2]
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movu m0, [lq+mmsize*0+4]
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@ -1666,7 +1671,12 @@ cglobal vp9_ipred_hu_32x32_16, 3, 7, 10 + notcpuflag(ssse3), \
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SBUTTERFLY wd, 7, 6, 0
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pshufd m1, m1, q3333
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UNSCRATCH 0, 9, rsp+1*mmsize
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%if ARCH_X86_64 || HAVE_ALIGNED_STACK
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DEFINE_ARGS dst, stride, cnt, stride3, stride4, stride20, stride28
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%else
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DEFINE_ARGS dst, stride, stride3, stride4, stride20, stride28
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%define cntd dword r0m
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%endif
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lea stride3q, [strideq*3]
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lea stride4q, [strideq*4]
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lea stride28q, [stride4q*8]
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