mirror of https://git.ffmpeg.org/ffmpeg.git
x86/vc1dsp: Port vc1_*_hor_16b_shift2 to NASM format
Reviewed-by: Christophe Gisquet <christophe.gisquet@gmail.com>
This commit is contained in:
Timothy Gu
parent
ebf648d490
commit
bcc223523e
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@ -25,6 +25,7 @@
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cextern pw_4
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cextern pw_5
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cextern pw_9
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cextern pw_128
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section .text
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@ -319,6 +320,44 @@ cglobal vc1_h_loop_filter8, 3,5,8
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RET
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%if HAVE_MMX_INLINE
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; XXX some of these macros are not used right now, but they will in the future
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; when more functions are ported.
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%macro OP_PUT 2 ; dst, src
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%endmacro
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%macro OP_AVG 2 ; dst, src
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pavgb %1, %2
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%endmacro
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%macro NORMALIZE_MMX 1 ; shift
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paddw m3, m7 ; +bias-r
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paddw m4, m7 ; +bias-r
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psraw m3, %1
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psraw m4, %1
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%endmacro
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%macro TRANSFER_DO_PACK 2 ; op, dst
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packuswb m3, m4
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%1 m3, [%2]
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mova [%2], m3
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%endmacro
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%macro TRANSFER_DONT_PACK 2 ; op, dst
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%1 m3, [%2]
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%1 m3, [%2 + mmsize]
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mova [%2], m3
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mova [mmsize + %2], m4
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%endmacro
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; see MSPEL_FILTER13_CORE for use as UNPACK macro
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%macro DO_UNPACK 1 ; reg
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punpcklbw %1, m0
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%endmacro
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%macro DONT_UNPACK 1 ; reg
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%endmacro
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; Compute the rounder 32-r or 8-r and unpacks it to m7
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%macro LOAD_ROUNDER_MMX 1 ; round
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movd m7, %1
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@ -394,6 +433,57 @@ cglobal vc1_put_ver_16b_shift2, 4,7,0, dst, src, stride
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dec i
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jnz .loop
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REP_RET
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%undef rnd
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%undef shift
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%undef stride_neg2
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%undef stride_9minus4
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%undef i
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; void ff_vc1_*_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,
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; const int16_t *src, int rnd);
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; Data is already unpacked, so some operations can directly be made from
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; memory.
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%macro HOR_16B_SHIFT2 2 ; op, opname
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cglobal vc1_%2_hor_16b_shift2, 4, 5, 0, dst, stride, src, rnd, h
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mov hq, 8
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sub srcq, 2
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sub rndd, (-1+9+9-1) * 1024 ; add -1024 bias
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LOAD_ROUNDER_MMX rndq
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mova m5, [pw_9]
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mova m6, [pw_128]
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pxor m0, m0
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.loop:
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mova m1, [srcq + 2 * 0]
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mova m2, [srcq + 2 * 0 + mmsize]
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mova m3, [srcq + 2 * 1]
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mova m4, [srcq + 2 * 1 + mmsize]
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paddw m3, [srcq + 2 * 2]
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paddw m4, [srcq + 2 * 2 + mmsize]
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paddw m1, [srcq + 2 * 3]
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paddw m2, [srcq + 2 * 3 + mmsize]
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pmullw m3, m5
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pmullw m4, m5
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psubw m3, m1
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psubw m4, m2
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NORMALIZE_MMX 7
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; remove bias
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paddw m3, m6
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paddw m4, m6
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TRANSFER_DO_PACK %1, dstq
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add srcq, 24
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add dstq, strideq
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dec hq
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jnz .loop
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RET
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%endmacro
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INIT_MMX mmx
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HOR_16B_SHIFT2 OP_PUT, put
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INIT_MMX mmxext
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HOR_16B_SHIFT2 OP_AVG, avg
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%endif ; HAVE_MMX_INLINE
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%macro INV_TRANS_INIT 0
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@ -38,6 +38,10 @@
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void ff_vc1_put_ver_16b_shift2_mmx(int16_t *dst,
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const uint8_t *src, x86_reg stride,
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int rnd, int64_t shift);
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void ff_vc1_put_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,
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const int16_t *src, int rnd);
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void ff_vc1_avg_hor_16b_shift2_mmxext(uint8_t *dst, x86_reg stride,
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const int16_t *src, int rnd);
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#define OP_PUT(S,D)
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#define OP_AVG(S,D) "pavgb " #S ", " #D " \n\t"
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@ -70,55 +74,6 @@ void ff_vc1_put_ver_16b_shift2_mmx(int16_t *dst,
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"punpcklwd %%mm7, %%mm7 \n\t" \
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"punpckldq %%mm7, %%mm7 \n\t"
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/**
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* Data is already unpacked, so some operations can directly be made from
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* memory.
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*/
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#define VC1_HOR_16b_SHIFT2(OP, OPNAME)\
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static void OPNAME ## vc1_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,\
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const int16_t *src, int rnd)\
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{\
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int h = 8;\
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\
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src -= 1;\
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rnd -= (-1+9+9-1)*1024; /* Add -1024 bias */\
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__asm__ volatile(\
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LOAD_ROUNDER_MMX("%4")\
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"movq "MANGLE(ff_pw_128)", %%mm6\n\t"\
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"movq "MANGLE(ff_pw_9)", %%mm5 \n\t"\
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"1: \n\t"\
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"movq 2*0+0(%1), %%mm1 \n\t"\
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"movq 2*0+8(%1), %%mm2 \n\t"\
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"movq 2*1+0(%1), %%mm3 \n\t"\
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"movq 2*1+8(%1), %%mm4 \n\t"\
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"paddw 2*3+0(%1), %%mm1 \n\t"\
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"paddw 2*3+8(%1), %%mm2 \n\t"\
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"paddw 2*2+0(%1), %%mm3 \n\t"\
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"paddw 2*2+8(%1), %%mm4 \n\t"\
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"pmullw %%mm5, %%mm3 \n\t"\
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"pmullw %%mm5, %%mm4 \n\t"\
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"psubw %%mm1, %%mm3 \n\t"\
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"psubw %%mm2, %%mm4 \n\t"\
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NORMALIZE_MMX("$7")\
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/* Remove bias */\
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"paddw %%mm6, %%mm3 \n\t"\
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"paddw %%mm6, %%mm4 \n\t"\
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TRANSFER_DO_PACK(OP)\
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"add $24, %1 \n\t"\
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"add %3, %2 \n\t"\
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"decl %0 \n\t"\
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"jnz 1b \n\t"\
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: "+r"(h), "+r" (src), "+r" (dst)\
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: "r"(stride), "m"(rnd)\
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NAMED_CONSTRAINTS_ADD(ff_pw_128,ff_pw_9)\
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: "memory"\
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);\
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}
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VC1_HOR_16b_SHIFT2(OP_PUT, put_)
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VC1_HOR_16b_SHIFT2(OP_AVG, avg_)
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/**
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* Purely vertical or horizontal 1/2 shift interpolation.
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* Sacrify mm6 for *9 factor.
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@ -380,14 +335,14 @@ typedef void (*vc1_mspel_mc_filter_8bits)(uint8_t *dst, const uint8_t *src, x86_
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* @param hmode Vertical filter.
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* @param rnd Rounding bias.
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*/
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#define VC1_MSPEL_MC(OP)\
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#define VC1_MSPEL_MC(OP, INSTR)\
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static void OP ## vc1_mspel_mc(uint8_t *dst, const uint8_t *src, int stride,\
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int hmode, int vmode, int rnd)\
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{\
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static const vc1_mspel_mc_filter_ver_16bits vc1_put_shift_ver_16bits[] =\
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{ NULL, vc1_put_ver_16b_shift1_mmx, ff_vc1_put_ver_16b_shift2_mmx, vc1_put_ver_16b_shift3_mmx };\
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static const vc1_mspel_mc_filter_hor_16bits vc1_put_shift_hor_16bits[] =\
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{ NULL, OP ## vc1_hor_16b_shift1_mmx, OP ## vc1_hor_16b_shift2_mmx, OP ## vc1_hor_16b_shift3_mmx };\
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{ NULL, OP ## vc1_hor_16b_shift1_mmx, ff_vc1_ ## OP ## hor_16b_shift2_ ## INSTR, OP ## vc1_hor_16b_shift3_mmx };\
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static const vc1_mspel_mc_filter_8bits vc1_put_shift_8bits[] =\
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{ NULL, OP ## vc1_shift1_mmx, OP ## vc1_shift2_mmx, OP ## vc1_shift3_mmx };\
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\
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@ -428,8 +383,8 @@ static void OP ## vc1_mspel_mc_16(uint8_t *dst, const uint8_t *src, \
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OP ## vc1_mspel_mc(dst + 8, src + 8, stride, hmode, vmode, rnd); \
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}
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VC1_MSPEL_MC(put_)
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VC1_MSPEL_MC(avg_)
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VC1_MSPEL_MC(put_, mmx)
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VC1_MSPEL_MC(avg_, mmxext)
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/** Macro to ease bicubic filter interpolation functions declarations */
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#define DECLARE_FUNCTION(a, b) \
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