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mips: intreadwrite: remove unnecessary inline asm
GCC actually handles unaligned accesses correctly in all cases except, absurdly, 32-bit loads on mips64. The remaining asm is thus not needed, and removing it results in better code. Signed-off-by: Mans Rullgard <mans@mansr.com>
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@ -24,7 +24,7 @@
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#include <stdint.h>
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#include "config.h"
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#if HAVE_INLINE_ASM
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#if ARCH_MIPS64 && HAVE_INLINE_ASM
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#define AV_RN32 AV_RN32
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static av_always_inline uint32_t AV_RN32(const void *p)
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@ -38,61 +38,6 @@ static av_always_inline uint32_t AV_RN32(const void *p)
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return v;
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}
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#define AV_WN32 AV_WN32
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static av_always_inline void AV_WN32(void *p, uint32_t v)
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{
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__asm__ ("swl %2, %0 \n\t"
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"swr %2, %1 \n\t"
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: "=m"(*(uint32_t *)((uint8_t *)p+3*!HAVE_BIGENDIAN)),
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"=m"(*(uint32_t *)((uint8_t *)p+3*HAVE_BIGENDIAN))
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: "r"(v));
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}
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#if ARCH_MIPS64
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#define AV_RN64 AV_RN64
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static av_always_inline uint64_t AV_RN64(const void *p)
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{
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uint64_t v;
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__asm__ ("ldl %0, %1 \n\t"
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"ldr %0, %2 \n\t"
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: "=&r"(v)
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: "m"(*(const uint64_t *)((const uint8_t *)p+7*!HAVE_BIGENDIAN)),
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"m"(*(const uint64_t *)((const uint8_t *)p+7*HAVE_BIGENDIAN)));
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return v;
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}
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#define AV_WN64 AV_WN64
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static av_always_inline void AV_WN64(void *p, uint64_t v)
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{
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__asm__ ("sdl %2, %0 \n\t"
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"sdr %2, %1 \n\t"
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: "=m"(*(uint64_t *)((uint8_t *)p+7*!HAVE_BIGENDIAN)),
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"=m"(*(uint64_t *)((uint8_t *)p+7*HAVE_BIGENDIAN))
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: "r"(v));
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}
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#else
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#define AV_RN64 AV_RN64
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static av_always_inline uint64_t AV_RN64(const void *p)
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{
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union { uint64_t v; uint32_t hl[2]; } v;
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v.hl[0] = AV_RN32(p);
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v.hl[1] = AV_RN32((const uint8_t *)p + 4);
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return v.v;
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}
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#define AV_WN64 AV_WN64
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static av_always_inline void AV_WN64(void *p, uint64_t v)
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{
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union { uint64_t v; uint32_t hl[2]; } vv = { v };
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AV_WN32(p, vv.hl[0]);
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AV_WN32((uint8_t *)p + 4, vv.hl[1]);
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}
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#endif /* ARCH_MIPS64 */
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#endif /* HAVE_INLINE_ASM */
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#endif /* ARCH_MIPS64 && HAVE_INLINE_ASM */
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#endif /* AVUTIL_MIPS_INTREADWRITE_H */
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