mirror of https://git.ffmpeg.org/ffmpeg.git
ARM: convert VFP code to UAL syntax
Originally committed as revision 15994 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Måns Rullgård
parent
289e8fd001
commit
b0e8ce55ae
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@ -21,6 +21,7 @@
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#include "config.h"
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#include "asm.S"
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.fpu neon @ required for gas to accept UAL syntax
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/*
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* VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle
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* throughput for almost all the instructions (except for double precision
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@ -48,29 +49,29 @@ function ff_vector_fmul_vfp, export=1
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orr r12, r12, #(3 << 16) /* set vector size to 4 */
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fmxr fpscr, r12
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fldmias r3!, {s0-s3}
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fldmias r1!, {s8-s11}
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fldmias r3!, {s4-s7}
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fldmias r1!, {s12-s15}
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fmuls s8, s0, s8
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vldmia r3!, {s0-s3}
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vldmia r1!, {s8-s11}
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vldmia r3!, {s4-s7}
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vldmia r1!, {s12-s15}
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vmul.f32 s8, s0, s8
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1:
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subs r2, r2, #16
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fmuls s12, s4, s12
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fldmiasge r3!, {s16-s19}
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fldmiasge r1!, {s24-s27}
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fldmiasge r3!, {s20-s23}
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fldmiasge r1!, {s28-s31}
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fmulsge s24, s16, s24
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fstmias r0!, {s8-s11}
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fstmias r0!, {s12-s15}
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fmulsge s28, s20, s28
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fldmiasgt r3!, {s0-s3}
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fldmiasgt r1!, {s8-s11}
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fldmiasgt r3!, {s4-s7}
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fldmiasgt r1!, {s12-s15}
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fmulsge s8, s0, s8
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fstmiasge r0!, {s24-s27}
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fstmiasge r0!, {s28-s31}
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vmul.f32 s12, s4, s12
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vldmiage r3!, {s16-s19}
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vldmiage r1!, {s24-s27}
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vldmiage r3!, {s20-s23}
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vldmiage r1!, {s28-s31}
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vmulge.f32 s24, s16, s24
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vstmia r0!, {s8-s11}
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vstmia r0!, {s12-s15}
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vmulge.f32 s28, s20, s28
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vldmiagt r3!, {s0-s3}
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vldmiagt r1!, {s8-s11}
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vldmiagt r3!, {s4-s7}
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vldmiagt r1!, {s12-s15}
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vmulge.f32 s8, s0, s8
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vstmiage r0!, {s24-s27}
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vstmiage r0!, {s28-s31}
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bgt 1b
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bic r12, r12, #(7 << 16) /* set vector size back to 1 */
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@ -88,44 +89,44 @@ function ff_vector_fmul_vfp, export=1
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function ff_vector_fmul_reverse_vfp, export=1
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vpush {d8-d15}
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add r2, r2, r3, lsl #2
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fldmdbs r2!, {s0-s3}
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fldmias r1!, {s8-s11}
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fldmdbs r2!, {s4-s7}
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fldmias r1!, {s12-s15}
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fmuls s8, s3, s8
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fmuls s9, s2, s9
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fmuls s10, s1, s10
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fmuls s11, s0, s11
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vldmdb r2!, {s0-s3}
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vldmia r1!, {s8-s11}
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vldmdb r2!, {s4-s7}
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vldmia r1!, {s12-s15}
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vmul.f32 s8, s3, s8
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vmul.f32 s9, s2, s9
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vmul.f32 s10, s1, s10
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vmul.f32 s11, s0, s11
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1:
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subs r3, r3, #16
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fldmdbsge r2!, {s16-s19}
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fmuls s12, s7, s12
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fldmiasge r1!, {s24-s27}
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fmuls s13, s6, s13
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fldmdbsge r2!, {s20-s23}
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fmuls s14, s5, s14
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fldmiasge r1!, {s28-s31}
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fmuls s15, s4, s15
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fmulsge s24, s19, s24
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fldmdbsgt r2!, {s0-s3}
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fmulsge s25, s18, s25
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fstmias r0!, {s8-s13}
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fmulsge s26, s17, s26
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fldmiasgt r1!, {s8-s11}
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fmulsge s27, s16, s27
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fmulsge s28, s23, s28
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fldmdbsgt r2!, {s4-s7}
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fmulsge s29, s22, s29
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fstmias r0!, {s14-s15}
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fmulsge s30, s21, s30
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fmulsge s31, s20, s31
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fmulsge s8, s3, s8
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fldmiasgt r1!, {s12-s15}
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fmulsge s9, s2, s9
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fmulsge s10, s1, s10
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fstmiasge r0!, {s24-s27}
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fmulsge s11, s0, s11
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fstmiasge r0!, {s28-s31}
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vldmdbge r2!, {s16-s19}
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vmul.f32 s12, s7, s12
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vldmiage r1!, {s24-s27}
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vmul.f32 s13, s6, s13
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vldmdbge r2!, {s20-s23}
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vmul.f32 s14, s5, s14
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vldmiage r1!, {s28-s31}
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vmul.f32 s15, s4, s15
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vmulge.f32 s24, s19, s24
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vldmdbgt r2!, {s0-s3}
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vmulge.f32 s25, s18, s25
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vstmia r0!, {s8-s13}
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vmulge.f32 s26, s17, s26
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vldmiagt r1!, {s8-s11}
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vmulge.f32 s27, s16, s27
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vmulge.f32 s28, s23, s28
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vldmdbgt r2!, {s4-s7}
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vmulge.f32 s29, s22, s29
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vstmia r0!, {s14-s15}
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vmulge.f32 s30, s21, s30
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vmulge.f32 s31, s20, s31
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vmulge.f32 s8, s3, s8
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vldmiagt r1!, {s12-s15}
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vmulge.f32 s9, s2, s9
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vmulge.f32 s10, s1, s10
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vstmiage r0!, {s24-s27}
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vmulge.f32 s11, s0, s11
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vstmiage r0!, {s28-s31}
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bgt 1b
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vpop {d8-d15}
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@ -143,36 +144,36 @@ function ff_vector_fmul_reverse_vfp, export=1
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function ff_float_to_int16_vfp, export=1
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push {r4-r8,lr}
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vpush {d8-d11}
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fldmias r1!, {s16-s23}
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ftosis s0, s16
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ftosis s1, s17
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ftosis s2, s18
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ftosis s3, s19
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ftosis s4, s20
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ftosis s5, s21
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ftosis s6, s22
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ftosis s7, s23
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vldmia r1!, {s16-s23}
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vcvt.s32.f32 s0, s16
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vcvt.s32.f32 s1, s17
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vcvt.s32.f32 s2, s18
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vcvt.s32.f32 s3, s19
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vcvt.s32.f32 s4, s20
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vcvt.s32.f32 s5, s21
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vcvt.s32.f32 s6, s22
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vcvt.s32.f32 s7, s23
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1:
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subs r2, r2, #8
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fmrrs r3, r4, {s0, s1}
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fmrrs r5, r6, {s2, s3}
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fmrrs r7, r8, {s4, s5}
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fmrrs ip, lr, {s6, s7}
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fldmiasgt r1!, {s16-s23}
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vmov r3, r4, s0, s1
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vmov r5, r6, s2, s3
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vmov r7, r8, s4, s5
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vmov ip, lr, s6, s7
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vldmiagt r1!, {s16-s23}
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ssat r4, #16, r4
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ssat r3, #16, r3
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ssat r6, #16, r6
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ssat r5, #16, r5
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pkhbt r3, r3, r4, lsl #16
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pkhbt r4, r5, r6, lsl #16
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ftosisgt s0, s16
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ftosisgt s1, s17
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ftosisgt s2, s18
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ftosisgt s3, s19
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ftosisgt s4, s20
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ftosisgt s5, s21
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ftosisgt s6, s22
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ftosisgt s7, s23
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vcvtgt.s32.f32 s0, s16
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vcvtgt.s32.f32 s1, s17
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vcvtgt.s32.f32 s2, s18
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vcvtgt.s32.f32 s3, s19
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vcvtgt.s32.f32 s4, s20
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vcvtgt.s32.f32 s5, s21
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vcvtgt.s32.f32 s6, s22
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vcvtgt.s32.f32 s7, s23
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ssat r8, #16, r8
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ssat r7, #16, r7
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ssat lr, #16, lr
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