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lavc/vp9dsp: R-V V mc bilin h v
C908 X60 vp9_avg_bilin_4h_8bpp_c : 5.5 4.7 vp9_avg_bilin_4h_8bpp_rvv_i32 : 1.7 1.5 vp9_avg_bilin_4v_8bpp_c : 5.5 4.7 vp9_avg_bilin_4v_8bpp_rvv_i32 : 1.5 1.2 vp9_avg_bilin_8h_8bpp_c : 20.0 17.7 vp9_avg_bilin_8h_8bpp_rvv_i32 : 3.0 2.7 vp9_avg_bilin_8v_8bpp_c : 20.7 18.7 vp9_avg_bilin_8v_8bpp_rvv_i32 : 3.0 2.7 vp9_avg_bilin_16h_8bpp_c : 78.2 69.7 vp9_avg_bilin_16h_8bpp_rvv_i32 : 7.0 6.2 vp9_avg_bilin_16v_8bpp_c : 98.5 73.2 vp9_avg_bilin_16v_8bpp_rvv_i32 : 7.0 6.0 vp9_avg_bilin_32h_8bpp_c : 325.5 275.5 vp9_avg_bilin_32h_8bpp_rvv_i32 : 23.0 20.5 vp9_avg_bilin_32v_8bpp_c : 342.2 290.0 vp9_avg_bilin_32v_8bpp_rvv_i32 : 21.7 19.5 vp9_avg_bilin_64h_8bpp_c : 1263.7 1095.7 vp9_avg_bilin_64h_8bpp_rvv_i32 : 91.2 81.2 vp9_avg_bilin_64v_8bpp_c : 1331.7 1155.2 vp9_avg_bilin_64v_8bpp_rvv_i32 : 91.2 81.0 vp9_put_bilin_4h_8bpp_c : 4.5 4.0 vp9_put_bilin_4h_8bpp_rvv_i32 : 1.0 1.0 vp9_put_bilin_4v_8bpp_c : 4.7 4.2 vp9_put_bilin_4v_8bpp_rvv_i32 : 1.0 1.0 vp9_put_bilin_8h_8bpp_c : 16.7 15.0 vp9_put_bilin_8h_8bpp_rvv_i32 : 2.2 2.0 vp9_put_bilin_8v_8bpp_c : 17.5 15.7 vp9_put_bilin_8v_8bpp_rvv_i32 : 2.2 2.0 vp9_put_bilin_16h_8bpp_c : 65.2 58.0 vp9_put_bilin_16h_8bpp_rvv_i32 : 6.0 5.5 vp9_put_bilin_16v_8bpp_c : 69.2 61.7 vp9_put_bilin_16v_8bpp_rvv_i32 : 5.7 5.2 vp9_put_bilin_32h_8bpp_c : 273.2 229.0 vp9_put_bilin_32h_8bpp_rvv_i32 : 19.7 17.7 vp9_put_bilin_32v_8bpp_c : 290.5 243.7 vp9_put_bilin_32v_8bpp_rvv_i32 : 18.7 16.7 vp9_put_bilin_64h_8bpp_c : 1040.5 910.5 vp9_put_bilin_64h_8bpp_rvv_i32 : 82.5 73.0 vp9_put_bilin_64v_8bpp_c : 1108.5 971.0 vp9_put_bilin_64v_8bpp_rvv_i32 : 82.2 73.2 Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
This commit is contained in:
sunyuechi
Rémi Denis-Courmont
parent
8f36c6f2e7
commit
9edd2e723b
@ -54,6 +54,111 @@ func ff_vp9_avg\len\()_rvv, zve32x
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endfunc
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.endm
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.macro bilin_load dst, mn, type
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.ifc \type,v
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add t4, a2, a3
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.else
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addi t4, a2, 1
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.endif
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vle8.v v4, (a2)
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vle8.v v0, (t4)
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vwmulu.vx v16, v0, \mn
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vwmaccsu.vx v16, t1, v4
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vwadd.wx v16, v16, t3
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vnsra.wi v16, v16, 4
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vadd.vv \dst, v16, v4
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add a2, a2, a3
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.endm
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.macro bilin_h_v op, type, mn
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func ff_\op\()_vp9_bilin_64\type\()_rvv, zve32x
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lpad 0
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vsetvlstatic8 64, t0, 64
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.ifc \op,avg
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csrwi vxrm, 0
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.endif
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li t3, 8
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neg t1, \mn
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1:
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addi a4, a4, -1
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bilin_load v0, \mn, \type
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.ifc \op,avg
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vle8.v v16, (a0)
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vaaddu.vv v0, v0, v16
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.endif
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vse8.v v0, (a0)
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add a0, a0, a1
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bnez a4, 1b
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ret
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.Lbilin_\type\op:
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.ifc \op,avg
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csrwi vxrm, 0
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.endif
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li t4, 8
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neg t1, \mn
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1:
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addi a4, a4, -2
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add t6, a0, a1
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add t0, a2, a3
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vle8.v v8, (a2)
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vle8.v v4, (t0)
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.ifc \type,v
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add t2, t0, a3
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vwmulu.vx v16, v4, \mn
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.else
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addi t3, a2, 1
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addi t2, t0, 1
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vle8.v v0, (t3)
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vwmulu.vx v16, v0, \mn
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.endif
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vle8.v v12, (t2)
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vwmulu.vx v20, v12, \mn
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vwmaccsu.vx v16, t1, v8
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vwmaccsu.vx v20, t1, v4
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vwadd.wx v16, v16, t4
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vwadd.wx v20, v20, t4
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vnsra.wi v16, v16, 4
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vnsra.wi v20, v20, 4
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vadd.vv v0, v16, v8
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vadd.vv v12, v20, v4
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.ifc \op,avg
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vle8.v v16, (a0)
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vle8.v v20, (t6)
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vaaddu.vv v0, v0, v16
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vaaddu.vv v12, v12, v20
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.endif
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vse8.v v0, (a0)
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vse8.v v12, (t6)
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add a2, t0, a3
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add a0, t6, a1
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bnez a4, 1b
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ret
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endfunc
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.endm
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.irp len, 64, 32, 16, 8, 4
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copy_avg \len
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.endr
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bilin_h_v put, h, a5
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bilin_h_v avg, h, a5
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bilin_h_v put, v, a6
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bilin_h_v avg, v, a6
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.macro func_bilin_h_v len, op, type
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func ff_\op\()_vp9_bilin_\len\()\type\()_rvv, zve32x
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lpad 0
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vsetvlstatic8 \len, t0, 64
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j .Lbilin_\type\()\op
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endfunc
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.endm
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.irp len, 32, 16, 8, 4
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.irp op, put, avg
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.irp type, h, v
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func_bilin_h_v \len, \op, \type
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.endr
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.endr
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.endr
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@ -107,27 +107,27 @@ void ff_avg_8tap_##type##_##SIZE##hv_rvv(uint8_t *dst, ptrdiff_t dststride, \
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int h, int mx, int my);
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#define VP9_BILINEAR_RISCV_RVV_FUNC(SIZE) \
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void ff_put_bilin_##SIZE##h_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_put_vp9_bilin_##SIZE##h_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my); \
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\
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void ff_put_bilin_##SIZE##v_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_put_vp9_bilin_##SIZE##v_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my); \
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\
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void ff_put_bilin_##SIZE##hv_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_put_vp9_bilin_##SIZE##hv_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my); \
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\
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void ff_avg_bilin_##SIZE##h_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_avg_vp9_bilin_##SIZE##h_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my); \
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\
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void ff_avg_bilin_##SIZE##v_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_avg_vp9_bilin_##SIZE##v_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my); \
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\
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void ff_avg_bilin_##SIZE##hv_rvv(uint8_t *dst, ptrdiff_t dststride, \
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void ff_avg_vp9_bilin_##SIZE##hv_rvv(uint8_t *dst, ptrdiff_t dststride, \
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const uint8_t *src, ptrdiff_t srcstride, \
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int h, int mx, int my);
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@ -63,6 +63,27 @@ static av_cold void vp9dsp_mc_init_riscv(VP9DSPContext *dsp, int bpp)
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init_fpel(3, 8);
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init_fpel(4, 4);
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dsp->mc[0][FILTER_BILINEAR ][0][0][1] = ff_put_vp9_bilin_64v_rvv;
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dsp->mc[0][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_64h_rvv;
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dsp->mc[0][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_64v_rvv;
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dsp->mc[0][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_64h_rvv;
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dsp->mc[1][FILTER_BILINEAR ][0][0][1] = ff_put_vp9_bilin_32v_rvv;
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dsp->mc[1][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_32h_rvv;
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dsp->mc[1][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_32v_rvv;
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dsp->mc[1][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_32h_rvv;
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dsp->mc[2][FILTER_BILINEAR ][0][0][1] = ff_put_vp9_bilin_16v_rvv;
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dsp->mc[2][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_16h_rvv;
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dsp->mc[2][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_16v_rvv;
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dsp->mc[2][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_16h_rvv;
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dsp->mc[3][FILTER_BILINEAR ][0][0][1] = ff_put_vp9_bilin_8v_rvv;
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dsp->mc[3][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_8h_rvv;
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dsp->mc[3][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_8v_rvv;
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dsp->mc[3][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_8h_rvv;
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dsp->mc[4][FILTER_BILINEAR ][0][0][1] = ff_put_vp9_bilin_4v_rvv;
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dsp->mc[4][FILTER_BILINEAR ][0][1][0] = ff_put_vp9_bilin_4h_rvv;
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dsp->mc[4][FILTER_BILINEAR ][1][0][1] = ff_avg_vp9_bilin_4v_rvv;
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dsp->mc[4][FILTER_BILINEAR ][1][1][0] = ff_avg_vp9_bilin_4h_rvv;
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#undef init_fpel
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}
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#endif
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