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lavc/me_cmp: R-V V vsse vsad intra
C908: vsad_4_c: 681.0 vsad_4_rvv_i32: 182.2 vsad_5_c: 278.0 vsad_5_rvv_i32: 145.2 vsse_4_c: 595.0 vsse_4_rvv_i32: 125.2 vsse_5_c: 281.0 vsse_5_rvv_i32: 101.2 Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
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@ -48,8 +48,12 @@ int ff_sse4_rvv(MpegEncContext *v, const uint8_t *pix1, const uint8_t *pix2,
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int ff_vsse16_rvv(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2, ptrdiff_t stride, int h);
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int ff_vsse8_rvv(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2, ptrdiff_t stride, int h);
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int ff_vsse_intra16_rvv(MpegEncContext *c, const uint8_t *s, const uint8_t *dummy, ptrdiff_t stride, int h);
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int ff_vsse_intra8_rvv(MpegEncContext *c, const uint8_t *s, const uint8_t *dummy, ptrdiff_t stride, int h);
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int ff_vsad16_rvv(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2, ptrdiff_t stride, int h);
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int ff_vsad8_rvv(MpegEncContext *c, const uint8_t *s1, const uint8_t *s2, ptrdiff_t stride, int h);
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int ff_vsad_intra16_rvv(MpegEncContext *c, const uint8_t *s, const uint8_t *dummy, ptrdiff_t stride, int h);
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int ff_vsad_intra8_rvv(MpegEncContext *c, const uint8_t *s, const uint8_t *dummy, ptrdiff_t stride, int h);
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av_cold void ff_me_cmp_init_riscv(MECmpContext *c, AVCodecContext *avctx)
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{
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@ -72,8 +76,12 @@ av_cold void ff_me_cmp_init_riscv(MECmpContext *c, AVCodecContext *avctx)
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c->vsse[0] = ff_vsse16_rvv;
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c->vsse[1] = ff_vsse8_rvv;
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c->vsse[4] = ff_vsse_intra16_rvv;
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c->vsse[5] = ff_vsse_intra8_rvv;
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c->vsad[0] = ff_vsad16_rvv;
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c->vsad[1] = ff_vsad8_rvv;
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c->vsad[4] = ff_vsad_intra16_rvv;
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c->vsad[5] = ff_vsad_intra8_rvv;
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}
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#endif
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}
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@ -314,6 +314,68 @@ endfunc
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ret
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.endm
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.macro vsad_vsse_intra16 type
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vsetivli t0, 16, e32, m4, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, m1, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (t1)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m2, tu, ma
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.ifc \type,abs
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vabsaddu v24, v16, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v16, v16
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.endif
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add a1, a1, a3
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add t1, t1, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m4, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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.macro vsad_vsse_intra8 type
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vsetivli t0, 8, e32, m2, ta, ma
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addi a4, a4, -1
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add t1, a1, a3
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vmv.v.x v24, zero
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vmv.s.x v0, zero
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1:
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vsetvli zero, zero, e8, mf2, tu, ma
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vle8.v v4, (a1)
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vle8.v v12, (t1)
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addi a4, a4, -1
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vwsubu.vv v16, v4, v12
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vsetvli zero, zero, e16, m1, tu, ma
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.ifc \type,abs
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vabsaddu v24, v16, v12
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.endif
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.ifc \type,square
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vwmacc.vv v24, v16, v16
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.endif
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add a1, a1, a3
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add t1, t1, a3
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bnez a4, 1b
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vsetvli zero, zero, e32, m2, tu, ma
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vredsum.vs v0, v24, v0
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vmv.x.s a0, v0
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ret
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.endm
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func ff_vsse16_rvv, zve32x
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vsad_vsse16 square
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endfunc
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@ -322,6 +384,14 @@ func ff_vsse8_rvv, zve32x
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vsad_vsse8 square
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endfunc
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func ff_vsse_intra16_rvv, zve32x
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vsad_vsse_intra16 square
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endfunc
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func ff_vsse_intra8_rvv, zve32x
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vsad_vsse_intra8 square
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endfunc
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func ff_vsad16_rvv, zve32x
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vsad_vsse16 abs
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endfunc
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@ -329,3 +399,11 @@ endfunc
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func ff_vsad8_rvv, zve32x
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vsad_vsse8 abs
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endfunc
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func ff_vsad_intra16_rvv, zve32x
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vsad_vsse_intra16 abs
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endfunc
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func ff_vsad_intra8_rvv, zve32x
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vsad_vsse_intra8 abs
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endfunc
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