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vp9/x86: idct_add_16x16_ssse3.
Currently only dc-only and full 16x16. Other subforms will follow in the near future. Total decoding time of ped1080p.webm goes from 9.7 to 9.3 seconds. DC-only goes from 957 -> 131 cycles, and the full IDCT goes from ~4050 to ~745 cycles.
This commit is contained in:
Ronald S. Bultje
parent
c65fe9e982
commit
8d4c616fc0
@ -153,6 +153,7 @@ filters_8tap_1d_fn3(avg)
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void ff_vp9_idct_idct_4x4_add_ssse3(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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void ff_vp9_idct_idct_8x8_add_ssse3(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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void ff_vp9_idct_idct_16x16_add_ssse3(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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#endif /* HAVE_YASM */
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@ -208,8 +209,10 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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init_subpel3(0, put, ssse3);
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init_subpel3(1, avg, ssse3);
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dsp->itxfm_add[TX_4X4][DCT_DCT] = ff_vp9_idct_idct_4x4_add_ssse3;
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if (ARCH_X86_64)
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if (ARCH_X86_64) {
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dsp->itxfm_add[TX_8X8][DCT_DCT] = ff_vp9_idct_idct_8x8_add_ssse3;
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dsp->itxfm_add[TX_16X16][DCT_DCT] = ff_vp9_idct_idct_16x16_add_ssse3;
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}
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}
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#undef init_fpel
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@ -2,6 +2,7 @@
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;* VP9 IDCT SIMD optimizations
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;*
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;* Copyright (C) 2013 Clément Bœsch <u pkh me>
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;* Copyright (C) 2013 Ronald S. Bultje <rsbultje gmail com>
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;*
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;* This file is part of FFmpeg.
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;*
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@ -26,24 +27,32 @@ SECTION_RODATA
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pw_11585x2: times 8 dw 23170
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%macro VP9_IDCT_COEFFS 2
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pw_m%1_%2: dw -%1, %2, -%1, %2, -%1, %2, -%1, %2
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pw_%2_%1: dw %2, %1, %2, %1, %2, %1, %2, %1
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%macro VP9_IDCT_COEFFS 2-3 0
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pw_m%1_%2: times 4 dw -%1, %2
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pw_%2_%1: times 4 dw %2, %1
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%if %3 == 1
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pw_m%2_m%1: times 4 dw -%2, -%1
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%endif
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%endmacro
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%macro VP9_IDCT_COEFFS_ALL 2
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%macro VP9_IDCT_COEFFS_ALL 2-3 0
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pw_%1x2: times 8 dw %1*2
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pw_%2x2: times 8 dw %2*2
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VP9_IDCT_COEFFS %1, %2
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VP9_IDCT_COEFFS %1, %2, %3
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%endmacro
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VP9_IDCT_COEFFS_ALL 15137, 6270
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VP9_IDCT_COEFFS_ALL 15137, 6270, 1
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VP9_IDCT_COEFFS_ALL 16069, 3196
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VP9_IDCT_COEFFS_ALL 9102, 13623
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VP9_IDCT_COEFFS_ALL 16305, 1606
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VP9_IDCT_COEFFS_ALL 10394, 12665
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VP9_IDCT_COEFFS_ALL 14449, 7723
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VP9_IDCT_COEFFS_ALL 4756, 15679
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pd_8192: times 4 dd 8192
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pw_2048: times 8 dw 2048
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pw_1024: times 8 dw 1024
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pw_512: times 8 dw 512
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SECTION .text
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@ -174,11 +183,12 @@ cglobal vp9_idct_idct_4x4_add, 4,4,0, dst, stride, block, eob
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VP9_IDCT4_WRITEOUT
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RET
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%if ARCH_X86_64 ; TODO: 32-bit? (32-bit limited to 8 xmm reg, we use more)
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;-------------------------------------------------------------------------------------------
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; void vp9_idct_idct_8x8_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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;-------------------------------------------------------------------------------------------
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%if ARCH_X86_64 ; TODO: 32-bit? (32-bit limited to 8 xmm reg, we use 13 here)
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%macro VP9_IDCT8_1D_FINALIZE 0
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SUMSUB_BA w, 3, 10, 4 ; m3=t0+t7, m10=t0-t7
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SUMSUB_BA w, 1, 2, 4 ; m1=t1+t6, m2=t1-t6
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@ -352,4 +362,257 @@ cglobal vp9_idct_idct_8x8_add, 4,4,13, dst, stride, block, eob
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mova [blockq+112], m4
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VP9_IDCT8_WRITEOUT
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RET
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%endif
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;---------------------------------------------------------------------------------------------
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; void vp9_idct_idct_16x16_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
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;---------------------------------------------------------------------------------------------
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%macro VP9_IDCT16_1D 2 ; src, pass
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mova m5, [%1+ 32] ; IN(1)
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mova m14, [%1+ 64] ; IN(2)
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mova m6, [%1+ 96] ; IN(3)
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mova m9, [%1+128] ; IN(4)
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mova m7, [%1+160] ; IN(5)
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mova m15, [%1+192] ; IN(6)
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mova m4, [%1+224] ; IN(7)
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mova m3, [%1+288] ; IN(9)
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mova m12, [%1+320] ; IN(10)
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mova m0, [%1+352] ; IN(11)
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mova m8, [%1+384] ; IN(12)
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mova m1, [%1+416] ; IN(13)
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mova m13, [%1+448] ; IN(14)
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mova m2, [%1+480] ; IN(15)
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; m10=in0, m5=in1, m14=in2, m6=in3, m9=in4, m7=in5, m15=in6, m4=in7
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; m11=in8, m3=in9, m12=in10 m0=in11, m8=in12, m1=in13, m13=in14, m2=in15
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VP9_UNPACK_MULSUB_2W_4X 9, 8, 15137, 6270, [pd_8192], 10, 11 ; t2, t3
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VP9_UNPACK_MULSUB_2W_4X 14, 13, 16069, 3196, [pd_8192], 10, 11 ; t4, t7
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VP9_UNPACK_MULSUB_2W_4X 12, 15, 9102, 13623, [pd_8192], 10, 11 ; t5, t6
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VP9_UNPACK_MULSUB_2W_4X 5, 2, 16305, 1606, [pd_8192], 10, 11 ; t8, t15
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VP9_UNPACK_MULSUB_2W_4X 3, 4, 10394, 12665, [pd_8192], 10, 11 ; t9, t14
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VP9_UNPACK_MULSUB_2W_4X 7, 0, 14449, 7723, [pd_8192], 10, 11 ; t10, t13
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VP9_UNPACK_MULSUB_2W_4X 1, 6, 4756, 15679, [pd_8192], 10, 11 ; t11, t12
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; m11=t0, m10=t1, m9=t2, m8=t3, m14=t4, m12=t5, m15=t6, m13=t7
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; m5=t8, m3=t9, m7=t10, m1=t11, m6=t12, m0=t13, m4=t14, m2=t15
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SUMSUB_BA w, 12, 14, 10 ; t4, t5
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SUMSUB_BA w, 15, 13, 10 ; t7, t6
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SUMSUB_BA w, 3, 5, 10 ; t8, t9
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SUMSUB_BA w, 7, 1, 10 ; t11, t10
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SUMSUB_BA w, 0, 6, 10 ; t12, t13
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SUMSUB_BA w, 4, 2, 10 ; t15, t14
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; m8=t0, m9=t1, m10=t2, m11=t3, m12=t4, m14=t5, m13=t6, m15=t7
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; m3=t8, m5=t9, m1=t10, m7=t11, m0=t12, m6=t13, m2=t14, m4=t15
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SUMSUB_BA w, 14, 13, 10
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pmulhrsw m13, [pw_11585x2] ; t5
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pmulhrsw m14, [pw_11585x2] ; t6
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VP9_UNPACK_MULSUB_2W_4X 2, 5, 15137, 6270, [pd_8192], 10, 11 ; t9, t14
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VP9_UNPACK_MULSUB_2W_4X 6, 1, 6270, m15137, [pd_8192], 10, 11 ; t10, t13
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; m8=t0, m9=t1, m10=t2, m11=t3, m12=t4, m13=t5, m14=t6, m15=t7
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; m3=t8, m2=t9, m6=t10, m7=t11, m0=t12, m1=t13, m5=t14, m4=t15
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SUMSUB_BA w, 7, 3, 10 ; t8, t11
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SUMSUB_BA w, 6, 2, 10 ; t9, t10
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SUMSUB_BA w, 0, 4, 10 ; t15, t12
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SUMSUB_BA w, 1, 5, 10 ; t14. t13
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; m15=t0, m14=t1, m13=t2, m12=t3, m11=t4, m10=t5, m9=t6, m8=t7
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; m7=t8, m6=t9, m2=t10, m3=t11, m4=t12, m5=t13, m1=t14, m0=t15
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SUMSUB_BA w, 2, 5, 10
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SUMSUB_BA w, 3, 4, 10
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pmulhrsw m5, [pw_11585x2] ; t10
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pmulhrsw m4, [pw_11585x2] ; t11
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pmulhrsw m3, [pw_11585x2] ; t12
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pmulhrsw m2, [pw_11585x2] ; t13
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; backup first register
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mova [rsp+32], m7
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; m15=t0, m14=t1, m13=t2, m12=t3, m11=t4, m10=t5, m9=t6, m8=t7
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; m7=t8, m6=t9, m5=t10, m4=t11, m3=t12, m2=t13, m1=t14, m0=t15
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; from load/start
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mova m10, [%1+ 0] ; IN(0)
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mova m11, [%1+256] ; IN(8)
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; from 3 stages back
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SUMSUB_BA w, 11, 10, 7
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pmulhrsw m11, [pw_11585x2] ; t0
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pmulhrsw m10, [pw_11585x2] ; t1
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; from 2 stages back
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SUMSUB_BA w, 8, 11, 7 ; t0, t3
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SUMSUB_BA w, 9, 10, 7 ; t1, t2
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; from 1 stage back
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SUMSUB_BA w, 15, 8, 7 ; t0, t7
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SUMSUB_BA w, 14, 9, 7 ; t1, t6
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SUMSUB_BA w, 13, 10, 7 ; t2, t5
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SUMSUB_BA w, 12, 11, 7 ; t3, t4
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SUMSUB_BA w, 0, 15, 7 ; t0, t15
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SUMSUB_BA w, 1, 14, 7 ; t1, t14
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SUMSUB_BA w, 2, 13, 7 ; t2, t13
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SUMSUB_BA w, 3, 12, 7 ; t3, t12
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SUMSUB_BA w, 4, 11, 7 ; t4, t11
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SUMSUB_BA w, 5, 10, 7 ; t5, t10
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%if %2 == 1
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; backup a different register
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mova [rsp+16], m15
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mova m7, [rsp+32]
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SUMSUB_BA w, 6, 9, 15 ; t6, t9
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SUMSUB_BA w, 7, 8, 15 ; t7, t8
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TRANSPOSE8x8W 0, 1, 2, 3, 4, 5, 6, 7, 15
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mova [rsp+ 0], m0
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mova [rsp+ 32], m1
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mova [rsp+ 64], m2
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mova [rsp+ 96], m3
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mova [rsp+128], m4
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mova [rsp+160], m5
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mova [rsp+192], m6
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mova [rsp+224], m7
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mova m15, [rsp+16]
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TRANSPOSE8x8W 8, 9, 10, 11, 12, 13, 14, 15, 0
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mova [rsp+ 16], m8
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mova [rsp+ 48], m9
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mova [rsp+ 80], m10
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mova [rsp+112], m11
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mova [rsp+144], m12
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mova [rsp+176], m13
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mova [rsp+208], m14
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mova [rsp+240], m15
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%else ; %2 == 2
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; backup more registers
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mova [rsp+64], m8
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mova [rsp+96], m9
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pxor m7, m7
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pmulhrsw m0, [pw_512]
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pmulhrsw m1, [pw_512]
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VP9_STORE_2X 0, 1, 8, 9, 7
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lea dstq, [dstq+strideq*2]
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pmulhrsw m2, [pw_512]
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pmulhrsw m3, [pw_512]
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VP9_STORE_2X 2, 3, 8, 9, 7
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lea dstq, [dstq+strideq*2]
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pmulhrsw m4, [pw_512]
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pmulhrsw m5, [pw_512]
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VP9_STORE_2X 4, 5, 8, 9, 7
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lea dstq, [dstq+strideq*2]
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; restore from cache
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SWAP 0, 7 ; move zero from m7 to m0
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mova m7, [rsp+32]
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mova m8, [rsp+64]
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mova m9, [rsp+96]
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SUMSUB_BA w, 6, 9, 1 ; t6, t9
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SUMSUB_BA w, 7, 8, 1 ; t7, t8
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pmulhrsw m6, [pw_512]
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pmulhrsw m7, [pw_512]
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VP9_STORE_2X 6, 7, 1, 2, 0
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lea dstq, [dstq+strideq*2]
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pmulhrsw m8, [pw_512]
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pmulhrsw m9, [pw_512]
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VP9_STORE_2X 8, 9, 1, 2, 0
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lea dstq, [dstq+strideq*2]
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pmulhrsw m10, [pw_512]
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pmulhrsw m11, [pw_512]
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VP9_STORE_2X 10, 11, 1, 2, 0
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lea dstq, [dstq+strideq*2]
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pmulhrsw m12, [pw_512]
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pmulhrsw m13, [pw_512]
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VP9_STORE_2X 12, 13, 1, 2, 0
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lea dstq, [dstq+strideq*2]
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pmulhrsw m14, [pw_512]
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pmulhrsw m15, [pw_512]
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VP9_STORE_2X 14, 15, 1, 2, 0
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%endif ; %2 == 1/2
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%endmacro
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%macro ZERO_BLOCK 3 ; mem, n_bytes, zero_reg
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%assign %%off 0
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%rep %2/mmsize
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mova [%1+%%off], %3
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%assign %%off (%%off+mmsize)
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%endrep
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%endmacro
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%macro VP9_STORE_2XFULL 6; dc, tmp1, tmp2, tmp3, tmp4, zero
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mova m%3, [dstq]
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mova m%5, [dstq+strideq]
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punpcklbw m%2, m%3, m%6
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punpckhbw m%3, m%6
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punpcklbw m%4, m%5, m%6
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punpckhbw m%5, m%6
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paddw m%2, m%1
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paddw m%3, m%1
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paddw m%4, m%1
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paddw m%5, m%1
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packuswb m%2, m%3
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packuswb m%4, m%5
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mova [dstq], m%2
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mova [dstq+strideq], m%4
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%endmacro
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INIT_XMM ssse3
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cglobal vp9_idct_idct_16x16_add, 4, 5, 16, 512, dst, stride, block, eob
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cmp eobd, 1 ; faster path for when only DC is set
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jne .idctfull
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; dc-only
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movd m0, [blockq]
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mova m1, [pw_11585x2]
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pmulhrsw m0, m1
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pmulhrsw m0, m1
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SPLATW m0, m0, q0000
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pmulhrsw m0, [pw_512]
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pxor m5, m5
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movd [blockq], m5
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%rep 7
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VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5
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lea dstq, [dstq+2*strideq]
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%endrep
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VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5
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RET
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.idctfull:
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DEFINE_ARGS dst, stride, block, cnt, dst_bak
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mov cntd, 2
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.loop1_full:
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VP9_IDCT16_1D blockq, 1
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add blockq, 16
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add rsp, 256
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dec cntd
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jg .loop1_full
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sub blockq, 32
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sub rsp, 512
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mov cntd, 2
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mov dst_bakq, dstq
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.loop2_full:
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VP9_IDCT16_1D rsp, 2
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lea dstq, [dst_bakq+8]
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add rsp, 16
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dec cntd
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jg .loop2_full
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sub rsp, 32
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; at the end of the loop, m0 should still be zero
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; use that to zero out block coefficients
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ZERO_BLOCK blockq, 512, m0
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RET
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%endif ; x86-64
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