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lavu/riscv: fix parsing the unaligned access capability 

Pointed-out-by: Stefan O'Rear <sorear@fastmail.com>
This commit is contained in:
Rémi Denis-Courmont 2024-05-14 23:13:12 +03:00
parent 0cc8661499
commit 83e5fdd3f4
1 changed files with 6 additions and 2 deletions
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6
libavutil/riscv/cpu.c
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@ -77,8 +77,12 @@ int ff_get_cpu_flags_riscv(void)
if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB) if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB)
ret |= AV_CPU_FLAG_RV_ZVBB; ret |= AV_CPU_FLAG_RV_ZVBB;
#endif #endif
if (pairs[2].value & RISCV_HWPROBE_MISALIGNED_FAST) switch (pairs[2].value & RISCV_HWPROBE_MISALIGNED_MASK) {
case RISCV_HWPROBE_MISALIGNED_FAST:
ret |= AV_CPU_FLAG_RV_MISALIGNED; ret |= AV_CPU_FLAG_RV_MISALIGNED;
break;
default:
}
} else } else
#endif #endif
#if HAVE_GETAUXVAL #if HAVE_GETAUXVAL