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lavc/opusdsp: RISC-V V (128-bit) postfilter
This is implemented for a vector size of 128-bit. Since the scalar product in the inner loop covers 5 samples or 160 bits, we need a group multipler of 2. To avoid reconfiguring the vector type, the outer loop, which loads multiple input samples sticks to the same multipler. Consequently, the outer loop loads 8 samples per iteration. This is safe since the minimum period of the CELT codec is 15 samples. The same code would also work, albeit needlessly inefficiently with a vector length of 256 bits. A proper implementation will follow instead.
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@ -58,6 +58,8 @@ av_cold void ff_opus_dsp_init(OpusDSP *ctx)
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#if ARCH_AARCH64
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ff_opus_dsp_init_aarch64(ctx);
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#elif ARCH_RISCV
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ff_opus_dsp_init_riscv(ctx);
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#elif ARCH_X86
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ff_opus_dsp_init_x86(ctx);
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#endif
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@ -30,5 +30,6 @@ void ff_opus_dsp_init(OpusDSP *ctx);
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void ff_opus_dsp_init_x86(OpusDSP *ctx);
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void ff_opus_dsp_init_aarch64(OpusDSP *ctx);
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void ff_opus_dsp_init_riscv(OpusDSP *ctx);
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#endif /* AVCODEC_OPUSDSP_H */
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@ -12,6 +12,8 @@ OBJS-$(CONFIG_FMTCONVERT) += riscv/fmtconvert_init.o
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RVV-OBJS-$(CONFIG_FMTCONVERT) += riscv/fmtconvert_rvv.o
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OBJS-$(CONFIG_IDCTDSP) += riscv/idctdsp_init.o
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RVV-OBJS-$(CONFIG_IDCTDSP) += riscv/idctdsp_rvv.o
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OBJS-$(CONFIG_OPUS_DECODER) += riscv/opusdsp_init.o
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RVV-OBJS-$(CONFIG_OPUS_DECODER) += riscv/opusdsp_rvv.o
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OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o \
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riscv/pixblockdsp_rvi.o
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RVV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvv.o
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42
libavcodec/riscv/opusdsp_init.c
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42
libavcodec/riscv/opusdsp_init.c
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@ -0,0 +1,42 @@
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/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/attributes.h"
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#include "libavutil/cpu.h"
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#include "libavutil/riscv/cpu.h"
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#include "libavcodec/opusdsp.h"
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void ff_opus_postfilter_rvv_128(float *data, int period, float *g, int len);
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av_cold void ff_opus_dsp_init_riscv(OpusDSP *d)
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{
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#if HAVE_RVV
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int flags = av_get_cpu_flags();
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if (flags & AV_CPU_FLAG_RVV_F32)
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switch (ff_get_rv_vlenb()) {
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case 16:
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d->postfilter = ff_opus_postfilter_rvv_128;
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break;
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}
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#endif
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}
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libavcodec/riscv/opusdsp_rvv.S
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57
libavcodec/riscv/opusdsp_rvv.S
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@ -0,0 +1,57 @@
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/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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func ff_opus_postfilter_rvv_128, zve32f
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addi a1, a1, 2
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slli a1, a1, 2
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lw t1, 4(a2)
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vsetivli zero, 3, e32, m1, ta, ma
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vle32.v v24, (a2)
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sub a1, a0, a1 // a1 = &x4 = &data[-(period + 2)]
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vsetivli zero, 5, e32, m2, ta, ma
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vslide1up.vx v8, v24, t1
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lw t2, 8(a2)
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vle32.v v16, (a1)
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vslide1up.vx v24, v8, t2 // v24 = { g[2], g[1], g[0], g[1], g[2] }
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2:
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vsetvli t0, a3, e32, m2, ta, ma
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vle32.v v0, (a0)
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sub a3, a3, t0
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3:
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vsetivli zero, 5, e32, m2, ta, ma
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lw t2, 20(a1)
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vfmul.vv v8, v24, v16
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addi a0, a0, 4
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vslide1down.vx v16, v16, t2
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addi a1, a1, 4
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vfredusum.vs v0, v8, v0
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vsetvli zero, t0, e32, m2, ta, ma
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vmv.x.s t1, v0
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addi t0, t0, -1
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vslide1down.vx v0, v0, zero
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sw t1, -4(a0)
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bnez t0, 3b
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bnez a3, 2b
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ret
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endfunc
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