From 7dde8be29fb7e27f2026e0d48d76eabc760de638 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Mon, 22 Jul 2024 22:17:40 +0300
Subject: [PATCH] checkasm/riscv: add forward-edge CFI landing pads

---
 tests/checkasm/riscv/checkasm.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/checkasm/riscv/checkasm.S b/tests/checkasm/riscv/checkasm.S
index 73ca85f344..835cc7d315 100644
--- a/tests/checkasm/riscv/checkasm.S
+++ b/tests/checkasm/riscv/checkasm.S
@@ -49,6 +49,7 @@ saved_regs:
         .endr
 
 func checkasm_set_function
+        lpad    0
         la.tls.ie t0, checked_func
         add     t0, tp, t0
         sd      a0, (t0)
@@ -56,6 +57,7 @@ func checkasm_set_function
 endfunc
 
 func checkasm_get_wrapper, v
+        lpad    0
         addi    sp, sp, -16
         sd      fp,  (sp)
         sd      ra, 8(sp)
@@ -74,6 +76,7 @@ func checkasm_get_wrapper, v
         ret
 
 2:      /* <-- Entry point with the Vector extension --> */
+        lpad    0
         /* Clobber the vectors */
         vsetvli t0, zero, e32, m8, ta, ma
         li      t0, 0xdeadbeef
@@ -90,6 +93,7 @@ func checkasm_get_wrapper, v
         csrwi   vxsat, 1     /* Saturation:    encountered */
 
 3:      /* <-- Entry point without the Vector extension --> */
+        lpad    0
         /* Save RA, unallocatable and callee-saved registers */
         la.tls.ie t0, saved_regs
         add     t0, tp, t0