mirror of https://git.ffmpeg.org/ffmpeg.git
avcodec/vvcdec: reuse h26x/2656_inter.asm to enable x86 optimizations
Signed-off-by: Wu Jianhua <toqsxw@outlook.com>
This commit is contained in:
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fc5ff6b0b8
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70889620f2
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@ -65,6 +65,7 @@ OBJS = ac3_parser.o \
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# subsystems
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include $(SRC_PATH)/libavcodec/vvc/Makefile
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include $(SRC_PATH)/libavcodec/x86/vvc/Makefile
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OBJS-$(CONFIG_AANDCTTABLES) += aandcttab.o
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OBJS-$(CONFIG_AC3DSP) += ac3dsp.o ac3.o ac3tab.o
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OBJS-$(CONFIG_ADTS_HEADER) += adts_header.o mpeg4audio_sample_rates.o
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@ -138,4 +138,8 @@ void ff_vvc_dsp_init(VVCDSPContext *vvcdsp, int bit_depth)
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VVC_DSP(8);
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break;
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}
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#if ARCH_X86
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ff_vvc_dsp_init_x86(vvcdsp, bit_depth);
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#endif
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}
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@ -167,4 +167,6 @@ typedef struct VVCDSPContext {
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void ff_vvc_dsp_init(VVCDSPContext *hpc, int bit_depth);
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void ff_vvc_dsp_init_x86(VVCDSPContext *hpc, const int bit_depth);
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#endif /* AVCODEC_VVC_VVCDSP_H */
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@ -0,0 +1,6 @@
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clean::
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$(RM) $(CLEANSUFFIXES:%=libavcodec/x86/vvc/%)
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OBJS-$(CONFIG_VVC_DECODER) += x86/vvc/vvcdsp_init.o
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X86ASM-OBJS-$(CONFIG_VVC_DECODER) += x86/h26x/h2656dsp.o \
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x86/h26x/h2656_inter.o
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@ -0,0 +1,202 @@
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/*
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* VVC DSP init for x86
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*
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* Copyright (C) 2022-2024 Nuo Mi
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* Copyright (c) 2023-2024 Wu Jianhua
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/cpu.h"
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#include "libavutil/x86/asm.h"
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#include "libavutil/x86/cpu.h"
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#include "libavcodec/vvc/vvcdec.h"
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#include "libavcodec/vvc/vvc_ctu.h"
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#include "libavcodec/vvc/vvcdsp.h"
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#include "libavcodec/x86/h26x/h2656dsp.h"
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#define FW_PUT(name, depth, opt) \
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static void ff_vvc_put_ ## name ## _ ## depth ## _##opt(int16_t *dst, const uint8_t *src, ptrdiff_t srcstride, \
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int height, const int8_t *hf, const int8_t *vf, int width) \
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{ \
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ff_h2656_put_## name ## _ ## depth ## _##opt(dst, 2 * MAX_PB_SIZE, src, srcstride, height, hf, vf, width); \
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}
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#define FW_PUT_TAP(fname, bitd, opt ) \
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FW_PUT(fname##4, bitd, opt ); \
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FW_PUT(fname##8, bitd, opt ); \
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FW_PUT(fname##16, bitd, opt ); \
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FW_PUT(fname##32, bitd, opt ); \
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FW_PUT(fname##64, bitd, opt ); \
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FW_PUT(fname##128, bitd, opt ); \
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#define FW_PUT_4TAP(fname, bitd, opt) \
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FW_PUT(fname ## 2, bitd, opt) \
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FW_PUT_TAP(fname, bitd, opt)
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#define FW_PUT_4TAP_SSE4(bitd) \
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FW_PUT_4TAP(pixels, bitd, sse4) \
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FW_PUT_4TAP(4tap_h, bitd, sse4) \
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FW_PUT_4TAP(4tap_v, bitd, sse4) \
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FW_PUT_4TAP(4tap_hv, bitd, sse4)
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#define FW_PUT_8TAP_SSE4(bitd) \
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FW_PUT_TAP(8tap_h, bitd, sse4) \
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FW_PUT_TAP(8tap_v, bitd, sse4) \
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FW_PUT_TAP(8tap_hv, bitd, sse4)
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#define FW_PUT_SSE4(bitd) \
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FW_PUT_4TAP_SSE4(bitd) \
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FW_PUT_8TAP_SSE4(bitd)
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FW_PUT_SSE4( 8);
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FW_PUT_SSE4(10);
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FW_PUT_SSE4(12);
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#define FW_PUT_TAP_AVX2(n, bitd) \
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FW_PUT(n ## tap_h32, bitd, avx2) \
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FW_PUT(n ## tap_h64, bitd, avx2) \
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FW_PUT(n ## tap_h128, bitd, avx2) \
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FW_PUT(n ## tap_v32, bitd, avx2) \
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FW_PUT(n ## tap_v64, bitd, avx2) \
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FW_PUT(n ## tap_v128, bitd, avx2)
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#define FW_PUT_AVX2(bitd) \
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FW_PUT(pixels32, bitd, avx2) \
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FW_PUT(pixels64, bitd, avx2) \
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FW_PUT(pixels128, bitd, avx2) \
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FW_PUT_TAP_AVX2(4, bitd) \
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FW_PUT_TAP_AVX2(8, bitd) \
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FW_PUT_AVX2( 8)
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FW_PUT_AVX2(10)
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FW_PUT_AVX2(12)
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#define FW_PUT_TAP_16BPC_AVX2(n, bitd) \
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FW_PUT(n ## tap_h16, bitd, avx2) \
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FW_PUT(n ## tap_v16, bitd, avx2) \
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FW_PUT(n ## tap_hv16, bitd, avx2) \
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FW_PUT(n ## tap_hv32, bitd, avx2) \
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FW_PUT(n ## tap_hv64, bitd, avx2) \
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FW_PUT(n ## tap_hv128, bitd, avx2)
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#define FW_PUT_16BPC_AVX2(bitd) \
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FW_PUT(pixels16, bitd, avx2) \
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FW_PUT_TAP_16BPC_AVX2(4, bitd) \
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FW_PUT_TAP_16BPC_AVX2(8, bitd);
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FW_PUT_16BPC_AVX2(10);
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FW_PUT_16BPC_AVX2(12);
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#define PEL_LINK(dst, C, W, idx1, idx2, name, D, opt) \
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dst[C][W][idx1][idx2] = ff_vvc_put_## name ## _ ## D ## _##opt; \
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dst ## _uni[C][W][idx1][idx2] = ff_h2656_put_uni_ ## name ## _ ## D ## _##opt; \
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#define MC_TAP_LINKS(pointer, C, my, mx, fname, bitd, opt ) \
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PEL_LINK(pointer, C, 1, my , mx , fname##4 , bitd, opt ); \
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PEL_LINK(pointer, C, 2, my , mx , fname##8 , bitd, opt ); \
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PEL_LINK(pointer, C, 3, my , mx , fname##16, bitd, opt ); \
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PEL_LINK(pointer, C, 4, my , mx , fname##32, bitd, opt ); \
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PEL_LINK(pointer, C, 5, my , mx , fname##64, bitd, opt ); \
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PEL_LINK(pointer, C, 6, my , mx , fname##128, bitd, opt );
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#define MC_8TAP_LINKS(pointer, my, mx, fname, bitd, opt) \
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MC_TAP_LINKS(pointer, LUMA, my, mx, fname, bitd, opt)
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#define MC_8TAP_LINKS_SSE4(bd) \
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MC_8TAP_LINKS(c->inter.put, 0, 0, pixels, bd, sse4); \
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MC_8TAP_LINKS(c->inter.put, 0, 1, 8tap_h, bd, sse4); \
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MC_8TAP_LINKS(c->inter.put, 1, 0, 8tap_v, bd, sse4); \
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MC_8TAP_LINKS(c->inter.put, 1, 1, 8tap_hv, bd, sse4)
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#define MC_4TAP_LINKS(pointer, my, mx, fname, bitd, opt) \
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PEL_LINK(pointer, CHROMA, 0, my , mx , fname##2 , bitd, opt ); \
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MC_TAP_LINKS(pointer, CHROMA, my, mx, fname, bitd, opt) \
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#define MC_4TAP_LINKS_SSE4(bd) \
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MC_4TAP_LINKS(c->inter.put, 0, 0, pixels, bd, sse4); \
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MC_4TAP_LINKS(c->inter.put, 0, 1, 4tap_h, bd, sse4); \
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MC_4TAP_LINKS(c->inter.put, 1, 0, 4tap_v, bd, sse4); \
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MC_4TAP_LINKS(c->inter.put, 1, 1, 4tap_hv, bd, sse4)
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#define MC_LINK_SSE4(bd) \
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MC_4TAP_LINKS_SSE4(bd) \
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MC_8TAP_LINKS_SSE4(bd)
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#define MC_TAP_LINKS_AVX2(C,tap,bd) do { \
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PEL_LINK(c->inter.put, C, 4, 0, 0, pixels32, bd, avx2) \
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PEL_LINK(c->inter.put, C, 5, 0, 0, pixels64, bd, avx2) \
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PEL_LINK(c->inter.put, C, 6, 0, 0, pixels128, bd, avx2) \
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PEL_LINK(c->inter.put, C, 4, 0, 1, tap##tap_h32, bd, avx2) \
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PEL_LINK(c->inter.put, C, 5, 0, 1, tap##tap_h64, bd, avx2) \
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PEL_LINK(c->inter.put, C, 6, 0, 1, tap##tap_h128, bd, avx2) \
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PEL_LINK(c->inter.put, C, 4, 1, 0, tap##tap_v32, bd, avx2) \
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PEL_LINK(c->inter.put, C, 5, 1, 0, tap##tap_v64, bd, avx2) \
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PEL_LINK(c->inter.put, C, 6, 1, 0, tap##tap_v128, bd, avx2) \
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} while (0)
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#define MC_LINKS_AVX2(bd) \
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MC_TAP_LINKS_AVX2(LUMA, 8, bd); \
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MC_TAP_LINKS_AVX2(CHROMA, 4, bd);
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#define MC_TAP_LINKS_16BPC_AVX2(C, tap, bd) do { \
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PEL_LINK(c->inter.put, C, 3, 0, 0, pixels16, bd, avx2) \
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PEL_LINK(c->inter.put, C, 3, 0, 1, tap##tap_h16, bd, avx2) \
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PEL_LINK(c->inter.put, C, 3, 1, 0, tap##tap_v16, bd, avx2) \
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PEL_LINK(c->inter.put, C, 3, 1, 1, tap##tap_hv16, bd, avx2) \
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PEL_LINK(c->inter.put, C, 4, 1, 1, tap##tap_hv32, bd, avx2) \
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PEL_LINK(c->inter.put, C, 5, 1, 1, tap##tap_hv64, bd, avx2) \
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PEL_LINK(c->inter.put, C, 6, 1, 1, tap##tap_hv128, bd, avx2) \
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} while (0)
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#define MC_LINKS_16BPC_AVX2(bd) \
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MC_TAP_LINKS_16BPC_AVX2(LUMA, 8, bd); \
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MC_TAP_LINKS_16BPC_AVX2(CHROMA, 4, bd);
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void ff_vvc_dsp_init_x86(VVCDSPContext *const c, const int bd)
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{
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const int cpu_flags = av_get_cpu_flags();
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if (ARCH_X86_64) {
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if (bd == 8) {
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if (EXTERNAL_SSE4(cpu_flags)) {
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MC_LINK_SSE4(8);
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}
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if (EXTERNAL_AVX2_FAST(cpu_flags)) {
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MC_LINKS_AVX2(8);
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}
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} else if (bd == 10) {
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if (EXTERNAL_SSE4(cpu_flags)) {
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MC_LINK_SSE4(10);
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}
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if (EXTERNAL_AVX2_FAST(cpu_flags)) {
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MC_LINKS_AVX2(10);
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MC_LINKS_16BPC_AVX2(10);
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}
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} else if (bd == 12) {
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if (EXTERNAL_SSE4(cpu_flags)) {
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MC_LINK_SSE4(12);
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}
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if (EXTERNAL_AVX2_FAST(cpu_flags)) {
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MC_LINKS_AVX2(12);
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MC_LINKS_16BPC_AVX2(12);
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}
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}
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}
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}
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