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lavc/vc1dsp: R-V V vc1_inv_trans_4x8
T-Head C908 (cycles): vc1dsp.vc1_inv_trans_4x8_c: 653.2 vc1dsp.vc1_inv_trans_4x8_rvv_i32: 234.0
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@ -28,6 +28,7 @@
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void ff_vc1_inv_trans_8x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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void ff_vc1_inv_trans_8x8_rvv(int16_t block[64]);
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void ff_vc1_inv_trans_4x8_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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void ff_vc1_inv_trans_4x8_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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void ff_vc1_inv_trans_8x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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void ff_vc1_inv_trans_8x4_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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void ff_vc1_inv_trans_4x4_dc_rvv(uint8_t *dest, ptrdiff_t stride, int16_t *block);
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@ -57,6 +58,7 @@ av_cold void ff_vc1dsp_init_riscv(VC1DSPContext *dsp)
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if (ff_rv_vlen_least(128)) {
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dsp->vc1_inv_trans_8x8 = ff_vc1_inv_trans_8x8_rvv;
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dsp->vc1_inv_trans_8x4 = ff_vc1_inv_trans_8x4_rvv;
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dsp->vc1_inv_trans_4x8 = ff_vc1_inv_trans_4x8_rvv;
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dsp->vc1_inv_trans_4x8_dc = ff_vc1_inv_trans_4x8_dc_rvv;
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dsp->vc1_inv_trans_4x4_dc = ff_vc1_inv_trans_4x4_dc_rvv;
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dsp->avg_vc1_mspel_pixels_tab[0][0] = ff_avg_pixels16x16_rvv;
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@ -296,6 +296,83 @@ func ff_vc1_inv_trans_8x4_rvv, zve32x
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ret
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endfunc
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func ff_vc1_inv_trans_4x8_rvv, zve32x
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li a3, 8 * 2
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csrwi vxrm, 0
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vsetivli zero, 8, e16, m1, ta, ma
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vlsseg4e16.v v0, (a2), a3
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li t1, 3
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jal t0, ff_vc1_inv_trans_4_rvv
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addi t1, a2, 1 * 8 * 2
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vse16.v v0, (a2)
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addi t2, a2, 2 * 8 * 2
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vse16.v v1, (t1)
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addi t3, a2, 3 * 8 * 2
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vse16.v v2, (t2)
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vse16.v v3, (t3)
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vsetivli zero, 4, e16, mf2, ta, ma
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vlseg8e16.v v0, (a2)
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jal t0, ff_vc1_inv_trans_8_rvv
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vadd.vi v4, v4, 1
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add t0, a1, a0
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vadd.vi v5, v5, 1
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vadd.vi v6, v6, 1
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add t1, a1, t0
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vadd.vi v7, v7, 1
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vssra.vi v0, v0, 7
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add t2, a1, t1
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vssra.vi v1, v1, 7
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vssra.vi v2, v2, 7
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add t3, a1, t2
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vssra.vi v3, v3, 7
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vssra.vi v4, v4, 7
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add t4, a1, t3
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vssra.vi v5, v5, 7
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vssra.vi v6, v6, 7
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add t5, a1, t4
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vssra.vi v7, v7, 7
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vle8.v v8, (a0)
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add t6, a1, t5
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vle8.v v9, (t0)
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vle8.v v10, (t1)
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vle8.v v11, (t2)
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vle8.v v12, (t3)
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vle8.v v13, (t4)
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vle8.v v14, (t5)
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vle8.v v15, (t6)
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vsetvli zero, zero, e8, mf4, ta, ma
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vwaddu.wv v0, v0, v8
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vwaddu.wv v1, v1, v9
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vwaddu.wv v2, v2, v10
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vwaddu.wv v3, v3, v11
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vwaddu.wv v4, v4, v12
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vwaddu.wv v5, v5, v13
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vwaddu.wv v6, v6, v14
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vwaddu.wv v7, v7, v15
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vsetvli zero, zero, e16, mf2, ta, ma
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.irp n,0,1,2,3,4,5,6,7
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vmax.vx v\n, v\n, zero
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.endr
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vsetvli zero, zero, e8, mf4, ta, ma
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vnclipu.wi v8, v0, 0
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vnclipu.wi v9, v1, 0
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vse8.v v8, (a0)
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vnclipu.wi v10, v2, 0
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vse8.v v9, (t0)
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vnclipu.wi v11, v3, 0
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vse8.v v10, (t1)
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vnclipu.wi v12, v4, 0
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vse8.v v11, (t2)
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vnclipu.wi v13, v5, 0
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vse8.v v12, (t3)
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vnclipu.wi v14, v6, 0
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vse8.v v13, (t4)
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vnclipu.wi v15, v7, 0
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vse8.v v14, (t5)
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vse8.v v15, (t6)
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ret
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endfunc
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.macro mspel_op op pos n1 n2
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add t1, \pos, a2
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v\op\()e8.v v\n1, (\pos)
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